| Message ID | 20211229023348.12606-12-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V RVV Zve32f and Zve64f extensions | expand |
On Wed, Dec 29, 2021 at 12:34 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 4 ++-- > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 2 +- > target/riscv/csr.c | 2 +- > target/riscv/translate.c | 2 ++ > 5 files changed, 7 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 38cd11a8ae..5e98860a09 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -562,8 +562,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > set_vext_version(env, vext_version); > } > - if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) { > - error_setg(errp, "Zve64f extension depends upon RVF."); > + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { > + error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); > return; > } > if (cpu->cfg.ext_j) { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d7b2db2b2f..3f3b3bb062 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -317,6 +317,7 @@ struct RISCVCPU { > bool ext_icsr; > bool ext_zfh; > bool ext_zfhmin; > + bool ext_zve32f; > bool ext_zve64f; > > char *priv_spec; > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 52d93a41fd..7d8b34cf1a 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -77,7 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, > *pc = env->pc; > *cs_base = 0; > > - if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) { > + if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { > /* > * If env->vl equals to VLMAX, we can use generic vector operation > * expanders (GVEC) to accerlate the vector operations. > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 340b9661a8..7bd3a5d1af 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno) > RISCVCPU *cpu = RISCV_CPU(cs); > > if (env->misa_ext & RVV || > - cpu->cfg.ext_zve64f) { > + cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { > #if !defined(CONFIG_USER_ONLY) > if (!env->debugger && !riscv_cpu_vector_enabled(env)) { > return RISCV_EXCP_ILLEGAL_INST; > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8c3b0168b7..3d89a6650d 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -78,6 +78,7 @@ typedef struct DisasContext { > bool ext_ifencei; > bool ext_zfh; > bool ext_zfhmin; > + bool ext_zve32f; > bool ext_zve64f; > bool hlsx; > /* vector extension */ > @@ -706,6 +707,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > ctx->ext_ifencei = cpu->cfg.ext_ifencei; > ctx->ext_zfh = cpu->cfg.ext_zfh; > ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; > + ctx->ext_zve32f = cpu->cfg.ext_zve32f; > ctx->ext_zve64f = cpu->cfg.ext_zve64f; > ctx->vlen = cpu->cfg.vlen; > ctx->elen = cpu->cfg.elen; > -- > 2.31.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 38cd11a8ae..5e98860a09 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -562,8 +562,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } set_vext_version(env, vext_version); } - if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) { - error_setg(errp, "Zve64f extension depends upon RVF."); + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); return; } if (cpu->cfg.ext_j) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d7b2db2b2f..3f3b3bb062 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -317,6 +317,7 @@ struct RISCVCPU { bool ext_icsr; bool ext_zfh; bool ext_zfhmin; + bool ext_zve32f; bool ext_zve64f; char *priv_spec; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 52d93a41fd..7d8b34cf1a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -77,7 +77,7 @@ void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; - if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve64f) { + if (riscv_has_ext(env, RVV) || cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { /* * If env->vl equals to VLMAX, we can use generic vector operation * expanders (GVEC) to accerlate the vector operations. diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 340b9661a8..7bd3a5d1af 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -51,7 +51,7 @@ static RISCVException vs(CPURISCVState *env, int csrno) RISCVCPU *cpu = RISCV_CPU(cs); if (env->misa_ext & RVV || - cpu->cfg.ext_zve64f) { + cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8c3b0168b7..3d89a6650d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -78,6 +78,7 @@ typedef struct DisasContext { bool ext_ifencei; bool ext_zfh; bool ext_zfhmin; + bool ext_zve32f; bool ext_zve64f; bool hlsx; /* vector extension */ @@ -706,6 +707,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->ext_ifencei = cpu->cfg.ext_ifencei; ctx->ext_zfh = cpu->cfg.ext_zfh; ctx->ext_zfhmin = cpu->cfg.ext_zfhmin; + ctx->ext_zve32f = cpu->cfg.ext_zve32f; ctx->ext_zve64f = cpu->cfg.ext_zve64f; ctx->vlen = cpu->cfg.vlen; ctx->elen = cpu->cfg.elen;