| Message ID | 20211229023348.12606-4-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V RVV Zve32f and Zve64f extensions | expand |
On Wed, Dec 29, 2021 at 12:34 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > All Zve* extensions support all vector load and store instructions, > except Zve64* extensions do not support EEW=64 for index values when > XLEN=32. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > --- > target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++++++++++---- > 1 file changed, 13 insertions(+), 4 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 5b47729a21..820a3387db 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, > uint8_t eew) > { > int8_t emul = eew - s->sew + s->lmul; > - return (emul >= -3 && emul <= 3) && > - require_align(vs2, emul) && > - require_align(vd, s->lmul) && > - require_nf(vd, nf, s->lmul); > + bool ret = (emul >= -3 && emul <= 3) && > + require_align(vs2, emul) && > + require_align(vd, s->lmul) && > + require_nf(vd, nf, s->lmul); > +#ifdef TARGET_RISCV32 Don't use hardcoded macros for this, instead use get_xl() Alistair > + /* > + * All Zve* extensions support all vector load and store instructions, > + * except Zve64* extensions do not support EEW=64 for index values > + * when XLEN=32. (Section 18.2) > + */ > + ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true); > +#endif > + return ret; > } > > /* > -- > 2.31.1 > >
On Tue, Jan 18, 2022 at 6:27 AM Alistair Francis <alistair23@gmail.com> wrote: > On Wed, Dec 29, 2021 at 12:34 PM <frank.chang@sifive.com> wrote: > > > > From: Frank Chang <frank.chang@sifive.com> > > > > All Zve* extensions support all vector load and store instructions, > > except Zve64* extensions do not support EEW=64 for index values when > > XLEN=32. > > > > Signed-off-by: Frank Chang <frank.chang@sifive.com> > > --- > > target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++++++++++---- > > 1 file changed, 13 insertions(+), 4 deletions(-) > > > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc > b/target/riscv/insn_trans/trans_rvv.c.inc > > index 5b47729a21..820a3387db 100644 > > --- a/target/riscv/insn_trans/trans_rvv.c.inc > > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > > @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, > int vd, int vs2, int nf, > > uint8_t eew) > > { > > int8_t emul = eew - s->sew + s->lmul; > > - return (emul >= -3 && emul <= 3) && > > - require_align(vs2, emul) && > > - require_align(vd, s->lmul) && > > - require_nf(vd, nf, s->lmul); > > + bool ret = (emul >= -3 && emul <= 3) && > > + require_align(vs2, emul) && > > + require_align(vd, s->lmul) && > > + require_nf(vd, nf, s->lmul); > > +#ifdef TARGET_RISCV32 > > Don't use hardcoded macros for this, instead use get_xl() > > Alistair > Thanks for the review. I'll fix it in my next revision patchset. Regards, Frank Chang > > > + /* > > + * All Zve* extensions support all vector load and store > instructions, > > + * except Zve64* extensions do not support EEW=64 for index values > > + * when XLEN=32. (Section 18.2) > > + */ > > + ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true); > > +#endif > > + return ret; > > } > > > > /* > > -- > > 2.31.1 > > > > >
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 5b47729a21..820a3387db 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -263,10 +263,19 @@ static bool vext_check_st_index(DisasContext *s, int vd, int vs2, int nf, uint8_t eew) { int8_t emul = eew - s->sew + s->lmul; - return (emul >= -3 && emul <= 3) && - require_align(vs2, emul) && - require_align(vd, s->lmul) && - require_nf(vd, nf, s->lmul); + bool ret = (emul >= -3 && emul <= 3) && + require_align(vs2, emul) && + require_align(vd, s->lmul) && + require_nf(vd, nf, s->lmul); +#ifdef TARGET_RISCV32 + /* + * All Zve* extensions support all vector load and store instructions, + * except Zve64* extensions do not support EEW=64 for index values + * when XLEN=32. (Section 18.2) + */ + ret &= (!has_ext(s, RVV) && s->ext_zve64f ? eew != MO_64 : true); +#endif + return ret; } /*