| Message ID | 20211229023348.12606-5-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add RISC-V RVV Zve32f and Zve64f extensions | expand |
On Wed, Dec 29, 2021 at 12:36 PM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > All Zve* extensions support all vector integer instructions, > except that the vmulh integer multiply variants that return the > high word of the product (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, > vmulhsu.vv, vmulhsu.vx) are not included for EEW=64 in Zve64*. > > Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++++++++++++++++++---- > 1 file changed, 33 insertions(+), 6 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 820a3387db..658cfbe10e 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -1906,14 +1906,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) > GEN_OPIVX_TRANS(vmax_vx, opivx_check) > > /* Vector Single-Width Integer Multiply Instructions */ > + > +static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a) > +{ > + /* > + * All Zve* extensions support all vector integer instructions, > + * except that the vmulh integer multiply variants > + * that return the high word of the product > + * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) > + * are not included for EEW=64 in Zve64*. (Section 18.2) > + */ > + return opivv_check(s, a) && > + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); > +} > + > +static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a) > +{ > + /* > + * All Zve* extensions support all vector integer instructions, > + * except that the vmulh integer multiply variants > + * that return the high word of the product > + * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) > + * are not included for EEW=64 in Zve64*. (Section 18.2) > + */ > + return opivx_check(s, a) && > + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); > +} > + > GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) > -GEN_OPIVV_TRANS(vmulh_vv, opivv_check) > -GEN_OPIVV_TRANS(vmulhu_vv, opivv_check) > -GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check) > +GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check) > +GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check) > +GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check) > GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) > -GEN_OPIVX_TRANS(vmulh_vx, opivx_check) > -GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) > -GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) > +GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check) > +GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check) > +GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check) > > /* Vector Integer Divide Instructions */ > GEN_OPIVV_TRANS(vdivu_vv, opivv_check) > -- > 2.31.1 > >
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 820a3387db..658cfbe10e 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1906,14 +1906,41 @@ GEN_OPIVX_TRANS(vmaxu_vx, opivx_check) GEN_OPIVX_TRANS(vmax_vx, opivx_check) /* Vector Single-Width Integer Multiply Instructions */ + +static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a) +{ + /* + * All Zve* extensions support all vector integer instructions, + * except that the vmulh integer multiply variants + * that return the high word of the product + * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) + * are not included for EEW=64 in Zve64*. (Section 18.2) + */ + return opivv_check(s, a) && + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); +} + +static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a) +{ + /* + * All Zve* extensions support all vector integer instructions, + * except that the vmulh integer multiply variants + * that return the high word of the product + * (vmulh.vv, vmulh.vx, vmulhu.vv, vmulhu.vx, vmulhsu.vv, vmulhsu.vx) + * are not included for EEW=64 in Zve64*. (Section 18.2) + */ + return opivx_check(s, a) && + (!has_ext(s, RVV) && s->ext_zve64f ? s->sew != MO_64 : true); +} + GEN_OPIVV_GVEC_TRANS(vmul_vv, mul) -GEN_OPIVV_TRANS(vmulh_vv, opivv_check) -GEN_OPIVV_TRANS(vmulhu_vv, opivv_check) -GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check) +GEN_OPIVV_TRANS(vmulh_vv, vmulh_vv_check) +GEN_OPIVV_TRANS(vmulhu_vv, vmulh_vv_check) +GEN_OPIVV_TRANS(vmulhsu_vv, vmulh_vv_check) GEN_OPIVX_GVEC_TRANS(vmul_vx, muls) -GEN_OPIVX_TRANS(vmulh_vx, opivx_check) -GEN_OPIVX_TRANS(vmulhu_vx, opivx_check) -GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check) +GEN_OPIVX_TRANS(vmulh_vx, vmulh_vx_check) +GEN_OPIVX_TRANS(vmulhu_vx, vmulh_vx_check) +GEN_OPIVX_TRANS(vmulhsu_vx, vmulh_vx_check) /* Vector Integer Divide Instructions */ GEN_OPIVV_TRANS(vdivu_vv, opivv_check)