diff mbox series

[v6,12/23] target/riscv: Implement AIA interrupt filtering CSRs

Message ID 20211230123539.52786-13-anup@brainfault.org (mailing list archive)
State New, archived
Headers show
Series QEMU RISC-V AIA support | expand

Commit Message

Anup Patel Dec. 30, 2021, 12:35 p.m. UTC
From: Anup Patel <anup.patel@wdc.com>

The AIA specificaiton adds interrupt filtering support for M-mode
and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
take local interrupt 13 or above and selectively inject same local
interrupt to lower privilege modes.

At the moment, we don't have any local interrupts above 12 so we
add dummy implementation (i.e. read zero and ignore write) of AIA
interrupt filtering CSRs.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

Comments

Frank Chang Jan. 11, 2022, 6 a.m. UTC | #1
Anup Patel <anup@brainfault.org> 於 2021年12月30日 週四 下午8:41寫道:

> From: Anup Patel <anup.patel@wdc.com>
>
> The AIA specificaiton adds interrupt filtering support for M-mode
> and HS-mode. Using AIA interrupt filtering M-mode and H-mode can
> take local interrupt 13 or above and selectively inject same local
> interrupt to lower privilege modes.
>
> At the moment, we don't have any local interrupts above 12 so we
> add dummy implementation (i.e. read zero and ignore write) of AIA
> interrupt filtering CSRs.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>
> Signed-off-by: Anup Patel <anup@brainfault.org>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/csr.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index decb0376fc..55e747fbf7 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -154,6 +154,15 @@ static RISCVException any32(CPURISCVState *env, int
> csrno)
>
>  }
>
> +static int aia_any(CPURISCVState *env, int csrno)
> +{
> +    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> +        return RISCV_EXCP_ILLEGAL_INST;
> +    }
> +
> +    return any(env, csrno);
> +}
> +
>  static int aia_any32(CPURISCVState *env, int csrno)
>  {
>      if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
> @@ -553,6 +562,12 @@ static RISCVException read_zero(CPURISCVState *env,
> int csrno,
>      return RISCV_EXCP_NONE;
>  }
>
> +static RISCVException write_ignore(CPURISCVState *env, int csrno,
> +                                   target_ulong val)
> +{
> +    return RISCV_EXCP_NONE;
> +}
> +
>  static RISCVException read_mhartid(CPURISCVState *env, int csrno,
>                                     target_ulong *val)
>  {
> @@ -2374,9 +2389,15 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
>      [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
>
> +    /* Virtual Interrupts for Supervisor Level (AIA) */
> +    [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
> +    [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
> +
>      /* Machine-Level High-Half CSRs (AIA) */
>      [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
>      [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
> +    [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
> +    [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
>      [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
>
>      /* Supervisor Trap Setup */
> @@ -2428,12 +2449,14 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>      [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,
> write_mtinst      },
>
>      /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA)
> */
> +    [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero,
> write_ignore },
>      [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl,
> write_hvictl },
>      [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,
>  write_hviprio1 },
>      [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,
>  write_hviprio2 },
>
>      /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
>      [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL,
> rmw_hidelegh },
> +    [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero,
> write_ignore },
>      [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL,
> rmw_hviph },
>      [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h,
> write_hviprio1h },
>      [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h,
> write_hviprio2h },
> --
> 2.25.1
>
>
>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index decb0376fc..55e747fbf7 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -154,6 +154,15 @@  static RISCVException any32(CPURISCVState *env, int csrno)
 
 }
 
+static int aia_any(CPURISCVState *env, int csrno)
+{
+    if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
+        return RISCV_EXCP_ILLEGAL_INST;
+    }
+
+    return any(env, csrno);
+}
+
 static int aia_any32(CPURISCVState *env, int csrno)
 {
     if (!riscv_feature(env, RISCV_FEATURE_AIA)) {
@@ -553,6 +562,12 @@  static RISCVException read_zero(CPURISCVState *env, int csrno,
     return RISCV_EXCP_NONE;
 }
 
+static RISCVException write_ignore(CPURISCVState *env, int csrno,
+                                   target_ulong val)
+{
+    return RISCV_EXCP_NONE;
+}
+
 static RISCVException read_mhartid(CPURISCVState *env, int csrno,
                                    target_ulong *val)
 {
@@ -2374,9 +2389,15 @@  riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTVAL]    = { "mtval",    any,  read_mtval,    write_mtval    },
     [CSR_MIP]      = { "mip",      any,  NULL,    NULL, rmw_mip        },
 
+    /* Virtual Interrupts for Supervisor Level (AIA) */
+    [CSR_MVIEN]      = { "mvien", aia_any, read_zero, write_ignore },
+    [CSR_MVIP]       = { "mvip",  aia_any, read_zero, write_ignore },
+
     /* Machine-Level High-Half CSRs (AIA) */
     [CSR_MIDELEGH] = { "midelegh", aia_any32, NULL, NULL, rmw_midelegh },
     [CSR_MIEH]     = { "mieh",     aia_any32, NULL, NULL, rmw_mieh     },
+    [CSR_MVIENH]   = { "mvienh",   aia_any32, read_zero,  write_ignore },
+    [CSR_MVIPH]    = { "mviph",    aia_any32, read_zero,  write_ignore },
     [CSR_MIPH]     = { "miph",     aia_any32, NULL, NULL, rmw_miph     },
 
     /* Supervisor Trap Setup */
@@ -2428,12 +2449,14 @@  riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
     [CSR_MTINST]      = { "mtinst",      hmode,   read_mtinst,      write_mtinst      },
 
     /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) */
+    [CSR_HVIEN]       = { "hvien",       aia_hmode, read_zero, write_ignore },
     [CSR_HVICTL]      = { "hvictl",      aia_hmode, read_hvictl, write_hvictl },
     [CSR_HVIPRIO1]    = { "hviprio1",    aia_hmode, read_hviprio1,   write_hviprio1 },
     [CSR_HVIPRIO2]    = { "hviprio2",    aia_hmode, read_hviprio2,   write_hviprio2 },
 
     /* Hypervisor and VS-Level High-Half CSRs (H-extension with AIA) */
     [CSR_HIDELEGH]    = { "hidelegh",    aia_hmode32, NULL, NULL, rmw_hidelegh },
+    [CSR_HVIENH]      = { "hvienh",      aia_hmode32, read_zero, write_ignore },
     [CSR_HVIPH]       = { "hviph",       aia_hmode32, NULL, NULL, rmw_hviph },
     [CSR_HVIPRIO1H]   = { "hviprio1h",   aia_hmode32, read_hviprio1h, write_hviprio1h },
     [CSR_HVIPRIO2H]   = { "hviprio2h",   aia_hmode32, read_hviprio2h, write_hviprio2h },