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Mon, 3 Jan 2022 22:08:08 +0000 (GMT) Received: from b03ledav004.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 81D1F7805F; Mon, 3 Jan 2022 22:08:06 +0000 (GMT) Received: from farosas.linux.ibm.com.com (unknown [9.211.145.159]) by b03ledav004.gho.boulder.ibm.com (Postfix) with ESMTP; Mon, 3 Jan 2022 22:08:06 +0000 (GMT) From: Fabiano Rosas To: qemu-devel@nongnu.org Subject: [PATCH 7/9] target/ppc: powerpc_excp: Move ILE setting into a function Date: Mon, 3 Jan 2022 19:07:44 -0300 Message-Id: <20220103220746.3916246-8-farosas@linux.ibm.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220103220746.3916246-1-farosas@linux.ibm.com> References: <20220103220746.3916246-1-farosas@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: cOIRucmhWSg5erZKh5gTzWp_IsIeIP1P X-Proofpoint-ORIG-GUID: I8ePvtZ1e-H9vvEHNi0VBxRGcr53gtfD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.11.62.513 definitions=2022-01-03_09,2022-01-01_01,2021-12-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 spamscore=0 clxscore=1015 mlxscore=0 priorityscore=1501 adultscore=0 malwarescore=0 bulkscore=0 mlxlogscore=756 lowpriorityscore=0 impostorscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2110150000 definitions=main-2201030147 Received-SPF: pass client-ip=148.163.156.1; envelope-from=farosas@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: 0 X-Spam_score: -0.1 X-Spam_bar: / X-Spam_report: (-0.1 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.henderson@linaro.org, danielhb413@gmail.com, qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Move the ILE code into a separate function similarly to what we do for AIL. This leaves the excp_model check behind because it will go away when we split powerpc_excp. Signed-off-by: Fabiano Rosas --- target/ppc/excp_helper.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index e56ddbe5d5..d7e087f2f6 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -290,6 +290,17 @@ static inline void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp_model, int excp, #endif } +static void ppc_excp_toggle_ile(PowerPCCPU *cpu, target_ulong *new_msr) +{ +#ifdef TARGET_PPC64 + if (ppc_interrupts_little_endian(cpu, !!(*new_msr & MSR_HVB))) { + *new_msr |= (target_ulong)1 << MSR_LE; + } else { + *new_msr &= ~((target_ulong)1 << MSR_LE); + } +#endif +} + static inline void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, target_ulong msr) { @@ -756,18 +767,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp) } /* - * Sort out endianness of interrupt, this differs depending on the - * CPU, the HV mode, etc... + * We preserve MSR_LE, but some CPUs can take interrupts in a + * different endianness. */ -#ifdef TARGET_PPC64 if (excp_model >= POWERPC_EXCP_970) { - if (ppc_interrupts_little_endian(cpu, !!(new_msr & MSR_HVB))) { - new_msr |= (target_ulong)1 << MSR_LE; - } else { - new_msr &= ~((target_ulong)1 << MSR_LE); - } + ppc_excp_toggle_ile(cpu, &new_msr); } -#endif #if defined(TARGET_PPC64) if (excp_model == POWERPC_EXCP_BOOKE) {