| Message ID | 20220105204029.4058500-6-farosas@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: powerpc_excp improvements (2/n) | expand |
On Wed, Jan 05, 2022 at 05:40:27PM -0300, Fabiano Rosas wrote: > Some CPUs set ILE via an MSR bit. We can make > ppc_interrupts_little_endian handle that case as well. Now we have a > centralized way of determining the endianness of interrupts. > > This change has no functional impact. > > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/ppc/cpu.h | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h > index a6fc857ad4..f99cd0ea92 100644 > --- a/target/ppc/cpu.h > +++ b/target/ppc/cpu.h > @@ -2733,7 +2733,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) > { > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); > CPUPPCState *env = &cpu->env; > - bool ile = false; > + bool ile; > > if (hv && env->has_hv_mode) { > if (is_isa300(pcc)) { > @@ -2744,6 +2744,8 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) > > } else if (pcc->lpcr_mask & LPCR_ILE) { > ile = !!(env->spr[SPR_LPCR] & LPCR_ILE); > + } else { > + ile = !!(msr_ile); > } > > return ile;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index a6fc857ad4..f99cd0ea92 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2733,7 +2733,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) { PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUPPCState *env = &cpu->env; - bool ile = false; + bool ile; if (hv && env->has_hv_mode) { if (is_isa300(pcc)) { @@ -2744,6 +2744,8 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv) } else if (pcc->lpcr_mask & LPCR_ILE) { ile = !!(env->spr[SPR_LPCR] & LPCR_ILE); + } else { + ile = !!(msr_ile); } return ile;
Some CPUs set ILE via an MSR bit. We can make ppc_interrupts_little_endian handle that case as well. Now we have a centralized way of determining the endianness of interrupts. This change has no functional impact. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/cpu.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)