| Message ID | 20220118184448.852996-3-farosas@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: powerpc_excp improvements [40x] (3/n) | expand |
On 1/18/22 19:44, Fabiano Rosas wrote: > The 405 MSR has the Machine Check Enable bit. We're making use of it > when dispatching Machine Check, so add the bit to the msr_mask. > > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Thanks, C. > --- > target/ppc/cpu_init.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index e63705b1c6..23a13036b2 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) > (1ull << MSR_EE) | > (1ull << MSR_PR) | > (1ull << MSR_FP) | > + (1ull << MSR_ME) | > (1ull << MSR_DWE) | > (1ull << MSR_DE) | > (1ull << MSR_IR) | >
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e63705b1c6..23a13036b2 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | + (1ull << MSR_ME) | (1ull << MSR_DWE) | (1ull << MSR_DE) | (1ull << MSR_IR) |
The 405 MSR has the Machine Check Enable bit. We're making use of it when dispatching Machine Check, so add the bit to the msr_mask. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/cpu_init.c | 1 + 1 file changed, 1 insertion(+)