[PULL,38/61] roms/opensbi: Remove ELF images

From: Anup Patel <apatel@ventanamicro.com>

IronPort-SDR: 
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IronPort-SDR: 
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WDCIronportException: Internal
From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <apatel@ventanamicro.com>,
 Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 38/61] roms/opensbi: Remove ELF images
Date: Fri, 21 Jan 2022 15:58:07 +1000
Message-Id: <20220121055830.3164408-39-alistair.francis@opensource.wdc.com>
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Message ID	20220121055830.3164408-39-alistair.francis@opensource.wdc.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org> IronPort-SDR: uODkHnJ8+K0sf1ZBsU0URPBG6I1SwxcQAkXYtQQZEI5SkBO2P6TWENMsNRUzTch6IrEzRs8XaK Bqj793+DR9Y7n2fcG1vgxi8OXkSI4s6kUclbGy5gTHlVw4QRq4+ovFbUV6img+84D1v6e96cKB Xsfx0QqYKqcUzP7TKfvctbmri3ApVszM/3/9e4A+wE3nHVClY0B/5Qp5DYZ6IcWfe6rrwZsCjF S05HgEQxFqdf/V8YlV9qIBVANDWojT/8eEu8V+3atWDQP/BMZSc4j+pZn+3EMu9p6Tir7JZtAb tMkJrWRFHvwSzNlTtJ3LKjAP IronPort-SDR: t32kWVkOVqxzrqK6N5Rb0hauKQcraV2+j3MVxlO9z+Ji+LHVFpmelzVgwKgUxaBr8zDWpk77ew tKPkgcS9focUAuMUIGyeaP2kBd5kKK3Blj7dJasUqaSmbMObJZhZ7g92eb7qfJIP8geJrQZNnq DWIstOg3WbKLCq9nH//63iJsTcADqlqNfJ2tqbUddq817B6K4y8/mVPuWBsdZWT6ysLn6nWNHa NOQoQNHVdj+jI1/gF6FdhuMAVhsDzetc5MAzgruuiVthImwxsgKOv29tnx44YJZ8hkDNXwkrDk cH4= WDCIronportException: Internal From: Alistair Francis <alistair.francis@opensource.wdc.com> To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel <apatel@ventanamicro.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bmeng.cn@gmail.com> Subject: [PULL 38/61] roms/opensbi: Remove ELF images Date: Fri, 21 Jan 2022 15:58:07 +1000 Message-Id: <20220121055830.3164408-39-alistair.francis@opensource.wdc.com> In-Reply-To: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com> References: <20220121055830.3164408-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=0135fdaf6=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	[PULL,01/61] hw: timer: ibex_timer: Fixup reading w/o register \| expand [PULL,01/61] hw: timer: ibex_timer: Fixup reading w/o register [PULL,02/61] riscv: opentitan: fixup plic stride len [PULL,03/61] hw: timer: ibex_timer: update/add reg address [PULL,04/61] update-linux-headers: Add asm-riscv/kvm.h [PULL,05/61] target/riscv: Add target/riscv/kvm.c to place the public kvm interface [PULL,06/61] target/riscv: Implement function kvm_arch_init_vcpu [PULL,07/61] target/riscv: Implement kvm_arch_get_registers [PULL,08/61] target/riscv: Implement kvm_arch_put_registers [PULL,09/61] target/riscv: Support start kernel directly by KVM [PULL,10/61] target/riscv: Support setting external interrupt by KVM [PULL,11/61] target/riscv: Handle KVM_EXIT_RISCV_SBI exit [PULL,12/61] target/riscv: Add host cpu type [PULL,13/61] target/riscv: Add kvm_riscv_get/put_regs_timer [PULL,14/61] target/riscv: Implement virtual time adjusting with vm state changing [PULL,15/61] target/riscv: Support virtual time context synchronization [PULL,16/61] target/riscv: enable riscv kvm accel [PULL,17/61] softmmu/device_tree: Silence compiler warning with --enable-sanitizers [PULL,18/61] softmmu/device_tree: Remove redundant pointer assignment [PULL,19/61] target/riscv: rvv-1.0: Add Zve64f extension into RISC-V [PULL,20/61] target/riscv: rvv-1.0: Add Zve64f support for configuration insns [PULL,21/61] target/riscv: rvv-1.0: Add Zve64f support for load and store insns [PULL,22/61] target/riscv: rvv-1.0: Add Zve64f support for vmulh variant insns [PULL,23/61] target/riscv: rvv-1.0: Add Zve64f support for vsmul.vv and vsmul.vx insns [PULL,24/61] target/riscv: rvv-1.0: Add Zve64f support for scalar fp insns [PULL,25/61] target/riscv: rvv-1.0: Add Zve64f support for single-width fp reduction insns [PULL,26/61] target/riscv: rvv-1.0: Add Zve64f support for widening type-convert insns [PULL,27/61] target/riscv: rvv-1.0: Add Zve64f support for narrowing type-convert insns [PULL,28/61] target/riscv: rvv-1.0: Allow Zve64f extension to be turned on [PULL,29/61] target/riscv: rvv-1.0: Add Zve32f extension into RISC-V [PULL,30/61] target/riscv: rvv-1.0: Add Zve32f support for configuration insns [PULL,31/61] target/riscv: rvv-1.0: Add Zve32f support for scalar fp insns [PULL,32/61] target/riscv: rvv-1.0: Add Zve32f support for single-width fp reduction insns [PULL,33/61] target/riscv: rvv-1.0: Add Zve32f support for widening type-convert insns [PULL,34/61] target/riscv: rvv-1.0: Add Zve32f support for narrowing type-convert insns [PULL,35/61] target/riscv: rvv-1.0: Allow Zve32f extension to be turned on [PULL,36/61] hw/riscv: spike: Allow using binary firmware as bios [PULL,37/61] hw/riscv: Remove macros for ELF BIOS image names [PULL,38/61] roms/opensbi: Remove ELF images [PULL,39/61] target/riscv: Adjust pmpcfg access with mxl [PULL,40/61] target/riscv: Don't save pc when exception return [PULL,41/61] target/riscv: Sign extend link reg for jal and jalr [PULL,42/61] target/riscv: Sign extend pc for different XLEN [PULL,43/61] target/riscv: Create xl field in env [PULL,44/61] target/riscv: Ignore the pc bits above XLEN [PULL,45/61] target/riscv: Extend pc for runtime pc write [PULL,46/61] target/riscv: Use gdb xml according to max mxlen [PULL,47/61] target/riscv: Relax debug check for pm write [PULL,48/61] target/riscv: Adjust csr write mask with XLEN [PULL,49/61] target/riscv: Create current pm fields in env [PULL,50/61] target/riscv: Alloc tcg global for cur_pm[mask\|base] [PULL,51/61] target/riscv: Calculate address according to XLEN [PULL,52/61] target/riscv: Split pm_enabled into mask and base [PULL,53/61] target/riscv: Split out the vill from vtype [PULL,54/61] target/riscv: Adjust vsetvl according to XLEN [PULL,55/61] target/riscv: Remove VILL field in VTYPE [PULL,56/61] target/riscv: Fix check range for first fault only [PULL,57/61] target/riscv: Adjust vector address with mask [PULL,58/61] target/riscv: Adjust scalar reg in vector with XLEN [PULL,59/61] target/riscv: Set default XLEN for hypervisor [PULL,60/61] target/riscv: Enable uxl field write [PULL,61/61] target/riscv: Relax UXL field for debugging

[PULL,38/61] roms/opensbi: Remove ELF images

Commit Message

Patch