| Message ID | 20220122182444.724087-7-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm_gicv3_its: Implement MOVI and MOVALL commands | expand |
On 1/23/22 05:24, Peter Maydell wrote: > The GICD_CTLR distributor register has enable bits which control > whether the different interrupt groups (Group 0, Non-secure Group 1 > and Secure Group 1) are forwarded to the CPU. We get this right for > traditional interrupts, but forgot to account for it when adding > LPIs. LPIs are always Group 1 NS and if the EnableGrp1NS bit is not > set we must not forward them to the CPU. > > Signed-off-by: Peter Maydell<peter.maydell@linaro.org> > --- > hw/intc/arm_gicv3.c | 1 + > 1 file changed, 1 insertion(+) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 715df5421dd..6d3c8ee231c 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -166,6 +166,7 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs) } if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable && + (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) && (cs->hpplpi.prio != 0xff)) { if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) { cs->hppi.irq = cs->hpplpi.irq;
The GICD_CTLR distributor register has enable bits which control whether the different interrupt groups (Group 0, Non-secure Group 1 and Secure Group 1) are forwarded to the CPU. We get this right for traditional interrupts, but forgot to account for it when adding LPIs. LPIs are always Group 1 NS and if the EnableGrp1NS bit is not set we must not forward them to the CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/intc/arm_gicv3.c | 1 + 1 file changed, 1 insertion(+)