[v2,14/40] bsd-user/arm/target_arch_cpu.h: Use force_sig_fault for EXCP_UDEF

Commit Message

Warner Losh Jan. 25, 2022, 1:29 a.m. UTC

Use force_sig_fault to implement unknown opcode. This just uninlines
that function, so simplify things by using it. Fold in EXCP_NOCP and
EXCP_INVSTATE, as is done in linux-user. Make a note about slight
differences with FreeBSD in case any of them turn out to be important
later.

Signed-off-by: Warner Losh <[e-mail]>
Reviewed-by: Peter Maydell <[e-mail]>
Reviewed-by: Richard Henderson <[e-mail]>
---
 bsd-user/arm/target_arch_cpu.h | 25 +++++++++++++------------
 1 file changed, 13 insertions(+), 12 deletions(-)

Comments

Richard Henderson Jan. 27, 2022, 6:27 a.m. UTC | #1

On 1/25/22 12:29, Warner Losh wrote:
> +        case EXCP_NOCP:
> +        case EXCP_INVSTATE:
> +            /*
> +             * See arm/arm/undefined.c undefinedinstruction();
> +             *
> +             * A number of details aren't emulated (they likely don't matter):
> +             * o Misaligned PC generates ILL_ILLADR

As I mentioned, misaligned pc will not come here for qemu.
In the Arm ARM, see aarch32/functions/registers/BXWritePC:

// For branches to an unaligned PC counter in A32 state, the processor takes the branch
// and does one of:
// * Forces the address to be aligned
// * Leaves the PC unaligned, meaning the target generates a PC Alignment fault.

The hardware will either refuse to allow bit 1 to be set when bit 0 is clear, OR it will 
generate a PREFETCH_DATA_ABORT for Alignment.

QEMU will do the latter.


Otherwise,
Reviewed-by: Richard Henderson <[e-mail]>


r~

Warner Losh Jan. 27, 2022, 3:40 p.m. UTC | #2

On Wed, Jan 26, 2022 at 11:27 PM Richard Henderson <
[e-mail]> wrote:

> On 1/25/22 12:29, Warner Losh wrote:
> > +        case EXCP_NOCP:
> > +        case EXCP_INVSTATE:
> > +            /*
> > +             * See arm/arm/undefined.c undefinedinstruction();
> > +             *
> > +             * A number of details aren't emulated (they likely don't
> matter):
> > +             * o Misaligned PC generates ILL_ILLADR
>
> As I mentioned, misaligned pc will not come here for qemu.
> In the Arm ARM, see aarch32/functions/registers/BXWritePC:
>
> // For branches to an unaligned PC counter in A32 state, the processor
> takes the branch
> // and does one of:
> // * Forces the address to be aligned
> // * Leaves the PC unaligned, meaning the target generates a PC Alignment
> fault.
>
> The hardware will either refuse to allow bit 1 to be set when bit 0 is
> clear, OR it will
> generate a PREFETCH_DATA_ABORT for Alignment.
>
> QEMU will do the latter.
>

Ah, right. I'd meant to update the comments and it slipped my mind. I'll
note
that this can't happen in qemu.


>
> Otherwise,
> Reviewed-by: Richard Henderson <[e-mail]>
>

Thanks for this (and all the other) review and feedback.

Warner




> r~
>

Patch

diff --git a/bsd-user/arm/target_arch_cpu.h b/bsd-user/arm/target_arch_cpu.h
index 905f13aa1b9..f4b72939b2d 100644
--- a/bsd-user/arm/target_arch_cpu.h
+++ b/bsd-user/arm/target_arch_cpu.h
@@ -51,18 +51,19 @@  static inline void target_cpu_loop(CPUARMState *env)
         process_queued_cpu_work(cs);
         switch (trapnr) {
         case EXCP_UDEF:
-            {
-                /* See arm/arm/undefined.c undefinedinstruction(); */
-                info.si_addr = env->regs[15];
-
-                /* illegal instruction */
-                info.si_signo = TARGET_SIGILL;
-                info.si_errno = 0;
-                info.si_code = TARGET_ILL_ILLOPC;
-                queue_signal(env, info.si_signo, &info);
-
-                /* TODO: What about instruction emulation? */
-            }
+        case EXCP_NOCP:
+        case EXCP_INVSTATE:
+            /*
+             * See arm/arm/undefined.c undefinedinstruction();
+             *
+             * A number of details aren't emulated (they likely don't matter):
+             * o Misaligned PC generates ILL_ILLADR
+             * o Thumb-2 instructions generate ILLADR
+             * o Both modes implement coprocessor instructions, which we don't
+             *   do here. FreeBSD just implements them for the VFP coprocessor
+             *   and special kernel breakpoints, trace points, dtrace, etc.
+             */
+            force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->regs[15]);
             break;
         case EXCP_SWI:
             {