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[83.50.83.154]) by smtp.gmail.com with ESMTPSA id l20sm21692354pfc.53.2022.02.09.15.01.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 09 Feb 2022 15:01:24 -0800 (PST) To: qemu-devel@nongnu.org Cc: Riku Voipio , Richard Henderson , Laurent Vivier , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 6/9] exec: Define MMUAccessType in 'exec/cpu-tlb.h' header Date: Thu, 10 Feb 2022 00:00:27 +0100 Message-Id: <20220209230030.93987-7-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220209230030.93987-1-f4bug@amsat.org> References: <20220209230030.93987-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102c (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x102c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.248, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To reduce the inclusion of "hw/core/cpu.h", extract MMUAccessType to its own "exec/cpu-tlb.h" header. Signed-off-by: Philippe Mathieu-Daudé --- include/exec/cpu-defs.h | 1 + include/exec/cpu-tlb.h | 16 ++++++++++++++++ include/exec/cpu_ldst.h | 1 + include/exec/exec-all.h | 3 +++ include/hw/core/cpu.h | 6 ------ include/hw/core/tcg-cpu-ops.h | 1 + target/arm/internals.h | 1 + target/mips/internal.h | 1 + target/ppc/internal.h | 2 ++ target/ppc/mmu-hash32.h | 2 ++ target/ppc/mmu-hash64.h | 2 ++ target/ppc/mmu-radix64.h | 2 ++ target/s390x/s390x-internal.h | 2 ++ 13 files changed, 34 insertions(+), 6 deletions(-) create mode 100644 include/exec/cpu-tlb.h diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index ba3cd32a1e..c7eefb8633 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -29,6 +29,7 @@ #include "exec/hwaddr.h" #endif #include "exec/memattrs.h" +#include "exec/cpu-tlb.h" #include "hw/core/cpu.h" #include "cpu-param.h" diff --git a/include/exec/cpu-tlb.h b/include/exec/cpu-tlb.h new file mode 100644 index 0000000000..dccf91a817 --- /dev/null +++ b/include/exec/cpu-tlb.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * cpu-tlb.h: MMUAccessType definitions + * + */ + +#ifndef EXEC_CPU_TLB_H +#define EXEC_CPU_TLB_H + +typedef enum MMUAccessType { + MMU_DATA_LOAD = 0, + MMU_DATA_STORE = 1, + MMU_INST_FETCH = 2 +} MMUAccessType; + +#endif diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5c999966de..3784316471 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -63,6 +63,7 @@ #define CPU_LDST_H #include "exec/memopidx.h" +#include "exec/cpu-tlb.h" #include "qemu/int128.h" #include "cpu.h" diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d2cb0981f4..537f465f54 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -381,6 +381,9 @@ static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, { } #endif + +#include "exec/cpu-tlb.h" + /** * probe_access: * @env: CPUArchState diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c9d41e4ece..0b844cbf27 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -55,12 +55,6 @@ typedef struct CPUClass CPUClass; DECLARE_CLASS_CHECKERS(CPUClass, CPU, TYPE_CPU) -typedef enum MMUAccessType { - MMU_DATA_LOAD = 0, - MMU_DATA_STORE = 1, - MMU_INST_FETCH = 2 -} MMUAccessType; - typedef struct CPUWatchpoint CPUWatchpoint; /* see tcg-cpu-ops.h */ diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e13898553a..2c81fff428 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -10,6 +10,7 @@ #ifndef TCG_CPU_OPS_H #define TCG_CPU_OPS_H +#include "exec/cpu-tlb.h" #include "hw/core/cpu.h" struct TCGCPUOps { diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f05748ea4..4c006aa6b4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -25,6 +25,7 @@ #ifndef TARGET_ARM_INTERNALS_H #define TARGET_ARM_INTERNALS_H +#include "exec/cpu-tlb.h" #include "hw/registerfields.h" #include "tcg/tcg-gvec-desc.h" #include "syndrome.h" diff --git a/target/mips/internal.h b/target/mips/internal.h index ac6e03e2f2..f0f885005f 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -8,6 +8,7 @@ #ifndef MIPS_INTERNAL_H #define MIPS_INTERNAL_H +#include "exec/cpu-tlb.h" #include "exec/memattrs.h" #ifdef CONFIG_TCG #include "tcg/tcg-internal.h" diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 6aa9484f34..20010f53e7 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -18,6 +18,8 @@ #ifndef PPC_INTERNAL_H #define PPC_INTERNAL_H +#include "exec/cpu-tlb.h" + #define FUNC_MASK(name, ret_type, size, max_val) \ static inline ret_type name(uint##size##_t start, \ uint##size##_t end) \ diff --git a/target/ppc/mmu-hash32.h b/target/ppc/mmu-hash32.h index 3892b693d6..c6fcdebac5 100644 --- a/target/ppc/mmu-hash32.h +++ b/target/ppc/mmu-hash32.h @@ -3,6 +3,8 @@ #ifndef CONFIG_USER_ONLY +#include "exec/cpu-tlb.h" + hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); bool ppc_hash32_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type, hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h index 1496955d38..002dc4aec7 100644 --- a/target/ppc/mmu-hash64.h +++ b/target/ppc/mmu-hash64.h @@ -3,6 +3,8 @@ #ifndef CONFIG_USER_ONLY +#include "exec/cpu-tlb.h" + #ifdef TARGET_PPC64 void dump_slb(PowerPCCPU *cpu); int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot, diff --git a/target/ppc/mmu-radix64.h b/target/ppc/mmu-radix64.h index 4c768aa5cc..601967ae82 100644 --- a/target/ppc/mmu-radix64.h +++ b/target/ppc/mmu-radix64.h @@ -3,6 +3,8 @@ #ifndef CONFIG_USER_ONLY +#include "exec/cpu-tlb.h" + /* Radix Quadrants */ #define R_EADDR_MASK 0x3FFFFFFFFFFFFFFF #define R_EADDR_VALID_MASK 0xC00FFFFFFFFFFFFF diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h index 6fc8cad2d5..b451b702d0 100644 --- a/target/s390x/s390x-internal.h +++ b/target/s390x/s390x-internal.h @@ -10,6 +10,8 @@ #ifndef S390X_INTERNAL_H #define S390X_INTERNAL_H +#include "exec/cpu-tlb.h" + #include "cpu.h" #ifndef CONFIG_USER_ONLY