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[83.50.68.71]) by smtp.gmail.com with ESMTPSA id 16sm17650365pje.34.2022.02.15.09.01.43 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Feb 2022 09:01:46 -0800 (PST) To: qemu-devel@nongnu.org Cc: Roman Bolshakov , Peter Maydell , Christian Schoenebeck , Akihiko Odaki , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Stefan Hajnoczi , Paolo Bonzini Subject: [PATCH v2 4/8] configure: Disable out-of-line atomic operations on Aarch64 Date: Tue, 15 Feb 2022 18:01:02 +0100 Message-Id: <20220215170106.95848-5-f4bug@amsat.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220215170106.95848-1-f4bug@amsat.org> References: <20220215170106.95848-1-f4bug@amsat.org> MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::434 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pf1-x434.google.com X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, PDS_HP_HELO_NORDNS=0.904, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Reply-to: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Original-From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= via From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= GCC 10.1 introduced the -moutline-atomics option on Aarch64. This options is enabled by default, and triggers a link failure: Undefined symbols for architecture arm64: "___aarch64_cas1_acq_rel", referenced from: _qmp_migrate_recover in migration_migration.c.o _cpu_atomic_cmpxchgb_mmu in accel_tcg_cputlb.c.o _cpu_atomic_fetch_sminb_mmu in accel_tcg_cputlb.c.o _cpu_atomic_fetch_uminb_mmu in accel_tcg_cputlb.c.o _cpu_atomic_fetch_smaxb_mmu in accel_tcg_cputlb.c.o _cpu_atomic_fetch_umaxb_mmu in accel_tcg_cputlb.c.o _cpu_atomic_smin_fetchb_mmu in accel_tcg_cputlb.c.o ... "___aarch64_ldadd4_acq_rel", referenced from: _multifd_recv_new_channel in migration_multifd.c.o _monitor_event in monitor_hmp.c.o _handle_hmp_command in monitor_hmp.c.o _colo_compare_finalize in net_colo-compare.c.o _flatview_unref in softmmu_memory.c.o _virtio_scsi_hotunplug in hw_scsi_virtio-scsi.c.o _tcg_register_thread in tcg_tcg.c.o ... "___aarch64_swp4_acq", referenced from: _qemu_spin_lock in softmmu_cpu-timers.c.o _cpu_get_ticks in softmmu_cpu-timers.c.o _qemu_spin_lock in softmmu_icount.c.o _cpu_exec in accel_tcg_cpu-exec.c.o _page_flush_tb_1.isra.0 in accel_tcg_translate-all.c.o _page_entry_lock in accel_tcg_translate-all.c.o _do_tb_phys_invalidate in accel_tcg_translate-all.c.o ... QEMU implements its own atomic operations using C11 builtin helpers. Disable the GCC out-of-line atomic ops. Signed-off-by: Philippe Mathieu-Daudé --- Cc: Stefan Hajnoczi Cc: Paolo Bonzini Clearly out of my understanding, but at least it links and the qtests pass. --- configure | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/configure b/configure index 06c03cebd3..3217aa22cb 100755 --- a/configure +++ b/configure @@ -2826,6 +2826,18 @@ else avx512f_opt="no" fi +######################################### +# Disable out-of-line atomic operations. + +case "$cpu" in + aarch64) + write_c_skeleton; + if compile_prog "$CPU_CFLAGS -Werror -mno-outline-atomics" "" ; then + CPU_CFLAGS="-mno-outline-atomics $CPU_CFLAGS" + fi + ;; +esac + ######################################## # check if __[u]int128_t is usable.