| Message ID | 20220219002518.1936806-11-atishp@rivosinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Improve PMU support | expand |
On Sat, Feb 19, 2022 at 10:33 AM Atish Patra <atishp@rivosinc.com> wrote: > > From: Atish Patra <atish.patra@wdc.com> > > Qemu can monitor the following cache related PMU events through > tlb_fill functions. > > 1. DTLB load/store miss > 3. ITLB prefetch miss > > Increment the PMU counter in tlb_fill function. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > Signed-off-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu_helper.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 746335bfd6b9..094d41ba07f7 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -21,10 +21,13 @@ > #include "qemu/log.h" > #include "qemu/main-loop.h" > #include "cpu.h" > +#include "pmu.h" > #include "exec/exec-all.h" > #include "tcg/tcg-op.h" > #include "trace.h" > #include "semihosting/common-semi.h" > +#include "cpu.h" > +#include "cpu_bits.h" > > int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) > { > @@ -1174,6 +1177,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, > riscv_raise_exception(env, cs->exception_index, retaddr); > } > > + > +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) > +{ > + enum riscv_pmu_event_idx pmu_event_type; > + > + switch (access_type) { > + case MMU_INST_FETCH: > + pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; > + break; > + case MMU_DATA_LOAD: > + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; > + break; > + case MMU_DATA_STORE: > + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; > + break; > + default: > + return; > + } > + > + riscv_pmu_incr_ctr(cpu, pmu_event_type); > +} > + > bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > MMUAccessType access_type, int mmu_idx, > bool probe, uintptr_t retaddr) > @@ -1270,6 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > } > } > } else { > + pmu_tlb_fill_incr_ctr(cpu, access_type); > /* Single stage lookup */ > ret = get_physical_address(env, &pa, &prot, address, NULL, > access_type, mmu_idx, true, false, false); > -- > 2.30.2 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 746335bfd6b9..094d41ba07f7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -21,10 +21,13 @@ #include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "pmu.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" +#include "cpu.h" +#include "cpu_bits.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { @@ -1174,6 +1177,28 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, riscv_raise_exception(env, cs->exception_index, retaddr); } + +static void pmu_tlb_fill_incr_ctr(RISCVCPU *cpu, MMUAccessType access_type) +{ + enum riscv_pmu_event_idx pmu_event_type; + + switch (access_type) { + case MMU_INST_FETCH: + pmu_event_type = RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS; + break; + case MMU_DATA_LOAD: + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS; + break; + case MMU_DATA_STORE: + pmu_event_type = RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS; + break; + default: + return; + } + + riscv_pmu_incr_ctr(cpu, pmu_event_type); +} + bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -1270,6 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, } } } else { + pmu_tlb_fill_incr_ctr(cpu, access_type); /* Single stage lookup */ ret = get_physical_address(env, &pa, &prot, address, NULL, access_type, mmu_idx, true, false, false);