diff mbox series

[v5,27/49] target/ppc: implement vrlqmi

Message ID 20220225210936.1749575-28-matheus.ferst@eldorado.org.br (mailing list archive)
State New, archived
Headers show
Series target/ppc: PowerISA Vector/VSX instruction batch | expand

Commit Message

Matheus K. Ferst Feb. 25, 2022, 9:09 p.m. UTC 
From: Matheus Ferst <matheus.ferst@eldorado.org.br>

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/insn32.decode            |  1 +
 target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++++++++----
 2 files changed, 18 insertions(+), 4 deletions(-)

Comments

Richard Henderson Feb. 25, 2022, 9:44 p.m. UTC | #1 
On 2/25/22 11:09, matheus.ferst@eldorado.org.br wrote:
> +        if (insert) {
> +            get_avr64(n, a->vrt, true);
> +            get_avr64(vrb, a->vrt, false);
> +            tcg_gen_not_i64(ah, ah);
> +            tcg_gen_not_i64(al, al);
> +            tcg_gen_and_i64(n, n, ah);
> +            tcg_gen_and_i64(vrb, vrb, al);

Two tcg_gen_andc_i64.

Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~
diff mbox series

Patch

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 87d482c5d9..abc2007129 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -495,6 +495,7 @@  VRLQ            000100 ..... ..... ..... 00000000101    @VX
 
 VRLWMI          000100 ..... ..... ..... 00010000101    @VX
 VRLDMI          000100 ..... ..... ..... 00011000101    @VX
+VRLQMI          000100 ..... ..... ..... 00001000101    @VX
 
 VRLWNM          000100 ..... ..... ..... 00110000101    @VX
 VRLDNM          000100 ..... ..... ..... 00111000101    @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index eb305e84da..352250fad0 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1109,7 +1109,8 @@  static void do_vrlq_mask(TCGv_i64 mh, TCGv_i64 ml, TCGv_i64 b, TCGv_i64 e)
     tcg_temp_free_i64(t1);
 }
 
-static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
+static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask,
+                                bool insert)
 {
     TCGv_i64 ah, al, vrb, n, t0, t1, zero = tcg_constant_i64(0);
 
@@ -1146,7 +1147,7 @@  static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
     tcg_gen_shri_i64(ah, ah, 1);
     tcg_gen_or_i64(t1, ah, t1);
 
-    if (mask) {
+    if (mask || insert) {
         tcg_gen_shri_i64(n, vrb, 8);
         tcg_gen_shri_i64(vrb, vrb, 16);
         tcg_gen_andi_i64(n, n, 0x7f);
@@ -1156,6 +1157,17 @@  static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
 
         tcg_gen_and_i64(t0, t0, ah);
         tcg_gen_and_i64(t1, t1, al);
+
+        if (insert) {
+            get_avr64(n, a->vrt, true);
+            get_avr64(vrb, a->vrt, false);
+            tcg_gen_not_i64(ah, ah);
+            tcg_gen_not_i64(al, al);
+            tcg_gen_and_i64(n, n, ah);
+            tcg_gen_and_i64(vrb, vrb, al);
+            tcg_gen_or_i64(t0, t0, n);
+            tcg_gen_or_i64(t1, t1, vrb);
+        }
     }
 
     set_avr64(a->vrt, t0, true);
@@ -1171,8 +1183,9 @@  static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
     return true;
 }
 
-TRANS(VRLQ, do_vector_rotl_quad, false)
-TRANS(VRLQNM, do_vector_rotl_quad, true)
+TRANS(VRLQ, do_vector_rotl_quad, false, false)
+TRANS(VRLQNM, do_vector_rotl_quad, true, false)
+TRANS(VRLQMI, do_vector_rotl_quad, false, true)
 
 #define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3)               \
 static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t,     \