From patchwork Fri Feb 25 21:09:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Matheus K. Ferst" X-Patchwork-Id: 12761042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDEC0C433EF for ; Fri, 25 Feb 2022 22:30:33 +0000 (UTC) Received: from localhost ([::1]:41900 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNj6e-0005K2-Qn for qemu-devel@archiver.kernel.org; Fri, 25 Feb 2022 17:30:32 -0500 Received: from eggs.gnu.org ([209.51.188.92]:35908) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNhyB-0001PL-8P; Fri, 25 Feb 2022 16:17:43 -0500 Received: from [187.72.171.209] (port=58124 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNhy7-0004qx-Nu; Fri, 25 Feb 2022 16:17:41 -0500 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 25 Feb 2022 18:10:01 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 206E58001D1; Fri, 25 Feb 2022 18:10:01 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v5 47/49] target/ppc: implement plxsd/pstxsd Date: Fri, 25 Feb 2022 18:09:34 -0300 Message-Id: <20220225210936.1749575-48-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220225210936.1749575-1-matheus.ferst@eldorado.org.br> References: <20220225210936.1749575-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 X-OriginalArrivalTime: 25 Feb 2022 21:10:01.0516 (UTC) FILETIME=[0D5916C0:01D82A8C] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass client-ip=187.72.171.209; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leandro Lupori , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, clg@kaod.org, Matheus Ferst , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Leandro Lupori Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode tree. Reviewed-by: Richard Henderson Signed-off-by: Leandro Lupori Signed-off-by: Matheus Ferst --- target/ppc/insn32.decode | 2 ++ target/ppc/insn64.decode | 10 ++++++ target/ppc/translate.c | 14 ++------ target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++++++++-- 4 files changed, 67 insertions(+), 14 deletions(-) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index fede42f5ce..37b6470503 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -602,6 +602,8 @@ VCLRRB 000100 ..... ..... ..... 00111001101 @VX # VSX Load/Store Instructions +LXSD 111001 ..... ..... .............. 10 @DS +STXSD 111101 ..... ..... .............. 10 @DS LXV 111101 ..... ..... ............ . 001 @DQ_TSX STXV 111101 ..... ..... ............ . 101 @DQ_TSX LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode index fdb859f62d..b7426f5b24 100644 --- a/target/ppc/insn64.decode +++ b/target/ppc/insn64.decode @@ -32,6 +32,10 @@ ...... ..... ra:5 ................ \ &PLS_D si=%pls_si rt=%rt_tsxp +@8LS_D ...... .. . .. r:1 .. .................. \ + ...... rt:5 ra:5 ................ \ + &PLS_D si=%pls_si + # Format 8RR:D %8rr_si 32:s16 0:16 %8rr_xt 16:1 21:5 @@ -180,6 +184,12 @@ PSTFD 000001 10 0--.-- .................. \ ### VSX instructions +PLXSD 000001 00 0--.-- .................. \ + 101010 ..... ..... ................ @8LS_D + +PSTXSD 000001 00 0--.-- .................. \ + 101110 ..... ..... ................ @8LS_D + PLXV 000001 00 0--.-- .................. \ 11001 ...... ..... ................ @8LS_D_TSX PSTXV 000001 00 0--.-- .................. \ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index b46a11386e..1ef2eeeead 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6668,7 +6668,7 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) #include "translate/branch-impl.c.inc" -/* Handles lfdp, lxsd, lxssp */ +/* Handles lfdp, lxssp */ static void gen_dform39(DisasContext *ctx) { switch (ctx->opcode & 0x3) { @@ -6677,11 +6677,6 @@ static void gen_dform39(DisasContext *ctx) return gen_lfdp(ctx); } break; - case 2: /* lxsd */ - if (ctx->insns_flags2 & PPC2_ISA300) { - return gen_lxsd(ctx); - } - break; case 3: /* lxssp */ if (ctx->insns_flags2 & PPC2_ISA300) { return gen_lxssp(ctx); @@ -6691,7 +6686,7 @@ static void gen_dform39(DisasContext *ctx) return gen_invalid(ctx); } -/* handles stfdp, lxv, stxsd, stxssp lxvx */ +/* handles stfdp, lxv, stxssp lxvx */ static void gen_dform3D(DisasContext *ctx) { if ((ctx->opcode & 3) != 1) { /* DS-FORM */ @@ -6701,11 +6696,6 @@ static void gen_dform3D(DisasContext *ctx) return gen_stfdp(ctx); } break; - case 2: /* stxsd */ - if (ctx->insns_flags2 & PPC2_ISA300) { - return gen_stxsd(ctx); - } - break; case 3: /* stxssp */ if (ctx->insns_flags2 & PPC2_ISA300) { return gen_stxssp(ctx); diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index 0344c47eed..a6e9417f2d 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -309,7 +309,6 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_i64(xth); \ } -VSX_LOAD_SCALAR_DS(lxsd, ld64_i64) VSX_LOAD_SCALAR_DS(lxssp, ld32fs) #define VSX_STORE_SCALAR(name, operation) \ @@ -482,7 +481,6 @@ static void gen_##name(DisasContext *ctx) \ tcg_temp_free_i64(xth); \ } -VSX_STORE_SCALAR_DS(stxsd, st64_i64) VSX_STORE_SCALAR_DS(stxssp, st32fs) static void gen_mfvsrwz(DisasContext *ctx) @@ -2298,6 +2296,57 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired) return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired); } +static bool do_lstxsd(DisasContext *ctx, int rt, int ra, TCGv displ, bool store) +{ + TCGv ea; + TCGv_i64 xt; + MemOp mop; + + if (store) { + REQUIRE_VECTOR(ctx); + } else { + REQUIRE_VSX(ctx); + } + + xt = tcg_temp_new_i64(); + mop = DEF_MEMOP(MO_UQ); + + gen_set_access_type(ctx, ACCESS_INT); + ea = do_ea_calc(ctx, ra, displ); + + if (store) { + get_cpu_vsr(xt, rt + 32, true); + tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop); + } else { + tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop); + set_cpu_vsr(rt + 32, xt, true); + set_cpu_vsr(rt + 32, tcg_constant_i64(0), false); + } + + tcg_temp_free(ea); + tcg_temp_free_i64(xt); + + return true; +} + +static bool do_lstxsd_DS(DisasContext *ctx, arg_D *a, bool store) +{ + return do_lstxsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store); +} + +static bool do_plstxsd_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store) +{ + arg_D d; + + if (!resolve_PLS_D(ctx, &d, a)) { + return true; + } + + return do_lstxsd(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store); +} + +TRANS_FLAGS2(ISA300, LXSD, do_lstxsd_DS, false) +TRANS_FLAGS2(ISA300, STXSD, do_lstxsd_DS, true) TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false) TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false) TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true) @@ -2306,6 +2355,8 @@ TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false) TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false) TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true) TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true) +TRANS64_FLAGS2(ISA310, PLXSD, do_plstxsd_PLS_D, false) +TRANS64_FLAGS2(ISA310, PSTXSD, do_plstxsd_PLS_D, true) TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false) TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false) TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)