diff mbox series

[v6,07/14] target/riscv: rvk: add support for zkne/zknd extension in RV64

Message ID 20220227142553.25815-8-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series support subsets of scalar crypto extension | expand

Commit Message

Weiwei Li Feb. 27, 2022, 2:25 p.m. UTC 
- add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions

Co-authored-by: Ruibo Lu <luruibo2000@163.com>
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
 target/riscv/crypto_helper.c            | 136 ++++++++++++++++++++++++
 target/riscv/helper.h                   |   8 ++
 target/riscv/insn32.decode              |  11 ++
 target/riscv/insn_trans/trans_rvk.c.inc | 102 ++++++++++++++++++
 4 files changed, 257 insertions(+)

Comments

Richard Henderson Feb. 27, 2022, 7:13 p.m. UTC | #1 
On 2/27/22 04:25, Weiwei Li wrote:
>   - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, aes64ks1i instructions
> 
> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
>   target/riscv/crypto_helper.c            | 136 ++++++++++++++++++++++++
>   target/riscv/helper.h                   |   8 ++
>   target/riscv/insn32.decode              |  11 ++
>   target/riscv/insn_trans/trans_rvk.c.inc | 102 ++++++++++++++++++
>   4 files changed, 257 insertions(+)
> 
> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
> index f5a5909538..9e56668627 100644
> --- a/target/riscv/crypto_helper.c
> +++ b/target/riscv/crypto_helper.c
> @@ -136,4 +136,140 @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
>   {
>       return aes32_operation(bs, rs1, rs2, false, false);
>   }
> +
> +static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
> +                                           bool enc, bool mix)
> +{
> +    uint64_t RS1 = rs1;
> +    uint64_t RS2 = rs2;
> +    uint64_t result;
> +    uint64_t temp;
> +    uint32_t col_0;
> +    uint32_t col_1;
> +
> +    if (enc) {
> +        temp = AES_SHIFROWS_LO(RS1, RS2);

Ah, those unused macros get used, and with the right type.

> +target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
> +{
> +    uint64_t RS1 = rs1;
> +    uint8_t round_consts[10] = {
> +        0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
> +    };

static const.

> +        temp = (temp >> 8) | (temp << 24); /* Rotate right by 8 */

rol32

> +DEF_HELPER_2(aes64esm, tl, tl, tl)
> +DEF_HELPER_2(aes64es, tl, tl, tl)
> +DEF_HELPER_2(aes64ds, tl, tl, tl)
> +DEF_HELPER_2(aes64dsm, tl, tl, tl)
> +DEF_HELPER_2(aes64ks2, tl, tl, tl)
> +DEF_HELPER_2(aes64ks1i, tl, tl, tl)
> +DEF_HELPER_1(aes64im, tl, tl)

DEF_HELPER_FLAGS.

> +%rnum      20:4
...
> +aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd

It is much better to put the field where it belongs,
especially for a one-off like this.

aes64ks1i   00 11000 1 rnum:4 rs1:5 001 rd:5 0010011

The whole of riscv needs a cleanup on this point.


> +static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
> +{
> +    REQUIRE_ZKNE(ctx);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> +
> +    gen_helper_aes64esm(dest, src1, src2);
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}
...
> +static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
> +{
> +    REQUIRE_ZKNE(ctx);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
> +
> +    gen_helper_aes64es(dest, src1, src2);
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}

gen_arith.

> +static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
> +static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
> +static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)

Likewise.

> +static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
> +{
> +    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
> +
> +    if (a->rnum > 0xA) {
> +        return false;
> +    }
> +
> +    TCGv rnum = tcg_const_tl(a->rnum);
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +
> +    gen_helper_aes64ks1i(dest, src1, rnum);
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    tcg_temp_free(rnum);
> +    return true;
> +}

tcg_constant_tl.

> +
> +static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
> +{
> +    REQUIRE_ZKND(ctx);
> +
> +    TCGv dest = dest_gpr(ctx, a->rd);
> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
> +
> +    gen_helper_aes64im(dest, src1);
> +    gen_set_gpr(ctx, a->rd, dest);
> +
> +    return true;
> +}

gen_unary.


r~
Weiwei Li Feb. 28, 2022, 3:10 a.m. UTC | #2 
在 2022/2/28 上午3:13, Richard Henderson 写道:
> On 2/27/22 04:25, Weiwei Li wrote:
>>   - add aes64dsm, aes64ds, aes64im, aes64es, aes64esm, aes64ks2, 
>> aes64ks1i instructions
>>
>> Co-authored-by: Ruibo Lu <luruibo2000@163.com>
>> Co-authored-by: Zewen Ye <lustrew@foxmail.com>
>> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
>> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
>> ---
>>   target/riscv/crypto_helper.c            | 136 ++++++++++++++++++++++++
>>   target/riscv/helper.h                   |   8 ++
>>   target/riscv/insn32.decode              |  11 ++
>>   target/riscv/insn_trans/trans_rvk.c.inc | 102 ++++++++++++++++++
>>   4 files changed, 257 insertions(+)
>>
>> diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
>> index f5a5909538..9e56668627 100644
>> --- a/target/riscv/crypto_helper.c
>> +++ b/target/riscv/crypto_helper.c
>> @@ -136,4 +136,140 @@ target_ulong HELPER(aes32dsi)(target_ulong rs1, 
>> target_ulong rs2,
>>   {
>>       return aes32_operation(bs, rs1, rs2, false, false);
>>   }
>> +
>> +static inline target_ulong aes64_operation(target_ulong rs1, 
>> target_ulong rs2,
>> +                                           bool enc, bool mix)
>> +{
>> +    uint64_t RS1 = rs1;
>> +    uint64_t RS2 = rs2;
>> +    uint64_t result;
>> +    uint64_t temp;
>> +    uint32_t col_0;
>> +    uint32_t col_1;
>> +
>> +    if (enc) {
>> +        temp = AES_SHIFROWS_LO(RS1, RS2);
>
> Ah, those unused macros get used, and with the right type.
>
>> +target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
>> +{
>> +    uint64_t RS1 = rs1;
>> +    uint8_t round_consts[10] = {
>> +        0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
>> +    };
>
> static const.
>
>> +        temp = (temp >> 8) | (temp << 24); /* Rotate right by 8 */
>
> rol32
>
>> +DEF_HELPER_2(aes64esm, tl, tl, tl)
>> +DEF_HELPER_2(aes64es, tl, tl, tl)
>> +DEF_HELPER_2(aes64ds, tl, tl, tl)
>> +DEF_HELPER_2(aes64dsm, tl, tl, tl)
>> +DEF_HELPER_2(aes64ks2, tl, tl, tl)
>> +DEF_HELPER_2(aes64ks1i, tl, tl, tl)
>> +DEF_HELPER_1(aes64im, tl, tl)
>
> DEF_HELPER_FLAGS.
>
>> +%rnum      20:4
> ...
>> +aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd
>
> It is much better to put the field where it belongs,
> especially for a one-off like this.
>
> aes64ks1i   00 11000 1 rnum:4 rs1:5 001 rd:5 0010011
>
> The whole of riscv needs a cleanup on this point.
>
>
>> +static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
>> +{
>> +    REQUIRE_ZKNE(ctx);
>> +
>> +    TCGv dest = dest_gpr(ctx, a->rd);
>> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
>> +
>> +    gen_helper_aes64esm(dest, src1, src2);
>> +    gen_set_gpr(ctx, a->rd, dest);
>> +
>> +    return true;
>> +}
> ...
>> +static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
>> +{
>> +    REQUIRE_ZKNE(ctx);
>> +
>> +    TCGv dest = dest_gpr(ctx, a->rd);
>> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> +    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
>> +
>> +    gen_helper_aes64es(dest, src1, src2);
>> +    gen_set_gpr(ctx, a->rd, dest);
>> +
>> +    return true;
>> +}
>
> gen_arith.
>
>> +static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
>> +static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
>> +static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
>
> Likewise.
>
>> +static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
>> +{
>> +    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
>> +
>> +    if (a->rnum > 0xA) {
>> +        return false;
>> +    }
>> +
>> +    TCGv rnum = tcg_const_tl(a->rnum);
>> +    TCGv dest = dest_gpr(ctx, a->rd);
>> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> +
>> +    gen_helper_aes64ks1i(dest, src1, rnum);
>> +    gen_set_gpr(ctx, a->rd, dest);
>> +
>> +    tcg_temp_free(rnum);
>> +    return true;
>> +}
>
> tcg_constant_tl.
>
>> +
>> +static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
>> +{
>> +    REQUIRE_ZKND(ctx);
>> +
>> +    TCGv dest = dest_gpr(ctx, a->rd);
>> +    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
>> +
>> +    gen_helper_aes64im(dest, src1);
>> +    gen_set_gpr(ctx, a->rd, dest);
>> +
>> +    return true;
>> +}
>
> gen_unary.
>
OK. I'll fix them. Thanks a lot.

Regards,

Weiwei Li

>
> r~
diff mbox series

Patch

diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c
index f5a5909538..9e56668627 100644
--- a/target/riscv/crypto_helper.c
+++ b/target/riscv/crypto_helper.c
@@ -136,4 +136,140 @@  target_ulong HELPER(aes32dsi)(target_ulong rs1, target_ulong rs2,
 {
     return aes32_operation(bs, rs1, rs2, false, false);
 }
+
+static inline target_ulong aes64_operation(target_ulong rs1, target_ulong rs2,
+                                           bool enc, bool mix)
+{
+    uint64_t RS1 = rs1;
+    uint64_t RS2 = rs2;
+    uint64_t result;
+    uint64_t temp;
+    uint32_t col_0;
+    uint32_t col_1;
+
+    if (enc) {
+        temp = AES_SHIFROWS_LO(RS1, RS2);
+        temp = (((uint64_t)AES_sbox[(temp >> 0) & 0xFF] << 0) |
+                ((uint64_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+                ((uint64_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+                ((uint64_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+                ((uint64_t)AES_sbox[(temp >> 32) & 0xFF] << 32) |
+                ((uint64_t)AES_sbox[(temp >> 40) & 0xFF] << 40) |
+                ((uint64_t)AES_sbox[(temp >> 48) & 0xFF] << 48) |
+                ((uint64_t)AES_sbox[(temp >> 56) & 0xFF] << 56));
+        if (mix) {
+            col_0 = temp & 0xFFFFFFFF;
+            col_1 = temp >> 32;
+
+            col_0 = AES_MIXCOLUMN(col_0);
+            col_1 = AES_MIXCOLUMN(col_1);
+
+            result = ((uint64_t)col_1 << 32) | col_0;
+        } else {
+            result = temp;
+        }
+    } else {
+        temp = AES_INVSHIFROWS_LO(RS1, RS2);
+        temp = (((uint64_t)AES_isbox[(temp >> 0) & 0xFF] << 0) |
+                ((uint64_t)AES_isbox[(temp >> 8) & 0xFF] << 8) |
+                ((uint64_t)AES_isbox[(temp >> 16) & 0xFF] << 16) |
+                ((uint64_t)AES_isbox[(temp >> 24) & 0xFF] << 24) |
+                ((uint64_t)AES_isbox[(temp >> 32) & 0xFF] << 32) |
+                ((uint64_t)AES_isbox[(temp >> 40) & 0xFF] << 40) |
+                ((uint64_t)AES_isbox[(temp >> 48) & 0xFF] << 48) |
+                ((uint64_t)AES_isbox[(temp >> 56) & 0xFF] << 56));
+        if (mix) {
+            col_0 = temp & 0xFFFFFFFF;
+            col_1 = temp >> 32;
+
+            col_0 = AES_INVMIXCOLUMN(col_0);
+            col_1 = AES_INVMIXCOLUMN(col_1);
+
+            result = ((uint64_t)col_1 << 32) | col_0;
+        } else {
+            result = temp;
+        }
+    }
+
+    return result;
+}
+
+target_ulong HELPER(aes64esm)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, true, true);
+}
+
+target_ulong HELPER(aes64es)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, true, false);
+}
+
+target_ulong HELPER(aes64ds)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, false, false);
+}
+
+target_ulong HELPER(aes64dsm)(target_ulong rs1, target_ulong rs2)
+{
+    return aes64_operation(rs1, rs2, false, true);
+}
+
+target_ulong HELPER(aes64ks2)(target_ulong rs1, target_ulong rs2)
+{
+    uint64_t RS1 = rs1;
+    uint64_t RS2 = rs2;
+    uint32_t rs1_hi = RS1 >> 32;
+    uint32_t rs2_lo = RS2;
+    uint32_t rs2_hi = RS2 >> 32;
+
+    uint32_t r_lo = (rs1_hi ^ rs2_lo);
+    uint32_t r_hi = (rs1_hi ^ rs2_lo ^ rs2_hi);
+    target_ulong result = ((uint64_t)r_hi << 32) | r_lo;
+
+    return result;
+}
+
+target_ulong HELPER(aes64ks1i)(target_ulong rs1, target_ulong rnum)
+{
+    uint64_t RS1 = rs1;
+    uint8_t round_consts[10] = {
+        0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36
+    };
+
+    uint8_t enc_rnum = rnum;
+    uint32_t temp = (RS1 >> 32) & 0xFFFFFFFF;
+    uint8_t rcon_ = 0;
+    target_ulong result;
+
+    if (enc_rnum != 0xA) {
+        temp = (temp >> 8) | (temp << 24); /* Rotate right by 8 */
+        rcon_ = round_consts[enc_rnum];
+    }
+
+    temp = ((uint32_t)AES_sbox[(temp >> 24) & 0xFF] << 24) |
+           ((uint32_t)AES_sbox[(temp >> 16) & 0xFF] << 16) |
+           ((uint32_t)AES_sbox[(temp >> 8) & 0xFF] << 8) |
+           ((uint32_t)AES_sbox[(temp >> 0) & 0xFF] << 0);
+
+    temp ^= rcon_;
+
+    result = ((uint64_t)temp << 32) | temp;
+
+    return result;
+}
+
+target_ulong HELPER(aes64im)(target_ulong rs1)
+{
+    uint64_t RS1 = rs1;
+    uint32_t col_0 = RS1 & 0xFFFFFFFF;
+    uint32_t col_1 = RS1 >> 32;
+    target_ulong result;
+
+    col_0 = AES_INVMIXCOLUMN(col_0);
+    col_1 = AES_INVMIXCOLUMN(col_1);
+
+    result = ((uint64_t)col_1 << 32) | col_0;
+
+    return result;
+}
 #undef sext_xlen
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 3681cb1218..040b771eb6 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1121,3 +1121,11 @@  DEF_HELPER_3(aes32esmi, tl, tl, tl, tl)
 DEF_HELPER_3(aes32esi, tl, tl, tl, tl)
 DEF_HELPER_3(aes32dsmi, tl, tl, tl, tl)
 DEF_HELPER_3(aes32dsi, tl, tl, tl, tl)
+
+DEF_HELPER_2(aes64esm, tl, tl, tl)
+DEF_HELPER_2(aes64es, tl, tl, tl)
+DEF_HELPER_2(aes64ds, tl, tl, tl)
+DEF_HELPER_2(aes64dsm, tl, tl, tl)
+DEF_HELPER_2(aes64ks2, tl, tl, tl)
+DEF_HELPER_2(aes64ks1i, tl, tl, tl)
+DEF_HELPER_1(aes64im, tl, tl)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 57ed51df8a..bf6a8797a2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -20,6 +20,7 @@ 
 %bs        30:2
 %rs3       27:5
 %rs2       20:5
+%rnum      20:4
 %rs1       15:5
 %rd        7:5
 %sh5       20:5
@@ -840,6 +841,16 @@  hinval_gvma       0110011 ..... ..... 000 00000 1110011 @hfence_gvma
 # *** RV32 Zknd Standard Extension ***
 aes32dsmi   .. 10111 ..... ..... 000 ..... 0110011 @k_aes
 aes32dsi    .. 10101 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zknd Standard Extension ***
+aes64dsm    00 11111 ..... ..... 000 ..... 0110011 @r
+aes64ds     00 11101 ..... ..... 000 ..... 0110011 @r
+aes64im     00 11000 00000 ..... 001 ..... 0010011 @r2
 # *** RV32 Zkne Standard Extension ***
 aes32esmi   .. 10011 ..... ..... 000 ..... 0110011 @k_aes
 aes32esi    .. 10001 ..... ..... 000 ..... 0110011 @k_aes
+# *** RV64 Zkne Standard Extension ***
+aes64es     00 11001 ..... ..... 000 ..... 0110011 @r
+aes64esm    00 11011 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zkne/zknd Standard Extension ***
+aes64ks2    01 11111 ..... ..... 000 ..... 0110011 @r
+aes64ks1i   00 11000 1.... ..... 001 ..... 0010011 %rnum %rs1 %rd
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc
index eecbc8bfa8..3dc855fd3c 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -45,6 +45,20 @@  static bool trans_aes32esmi(DisasContext *ctx, arg_aes32esmi *a)
     return true;
 }
 
+static bool trans_aes64esm(DisasContext *ctx, arg_aes64esm *a)
+{
+    REQUIRE_ZKNE(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    gen_helper_aes64esm(dest, src1, src2);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
 static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
 {
     REQUIRE_ZKNE(ctx);
@@ -61,6 +75,20 @@  static bool trans_aes32esi(DisasContext *ctx, arg_aes32esi *a)
     return true;
 }
 
+static bool trans_aes64es(DisasContext *ctx, arg_aes64es *a)
+{
+    REQUIRE_ZKNE(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    gen_helper_aes64es(dest, src1, src2);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
 static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
 {
     REQUIRE_ZKND(ctx);
@@ -77,6 +105,34 @@  static bool trans_aes32dsmi(DisasContext *ctx, arg_aes32dsmi *a)
     return true;
 }
 
+static bool trans_aes64dsm(DisasContext *ctx, arg_aes64dsm *a)
+{
+    REQUIRE_ZKND(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    gen_helper_aes64dsm(dest, src1, src2);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
+static bool trans_aes64ks2(DisasContext *ctx, arg_aes64ks2 *a)
+{
+    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    gen_helper_aes64ks2(dest, src1, src2);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
 static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
 {
     REQUIRE_ZKND(ctx);
@@ -92,3 +148,49 @@  static bool trans_aes32dsi(DisasContext *ctx, arg_aes32dsi *a)
     tcg_temp_free(bs);
     return true;
 }
+
+static bool trans_aes64ds(DisasContext *ctx, arg_aes64ds *a)
+{
+    REQUIRE_ZKND(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    gen_helper_aes64ds(dest, src1, src2);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}
+
+static bool trans_aes64ks1i(DisasContext *ctx, arg_aes64ks1i *a)
+{
+    REQUIRE_EITHER_EXT(ctx, zknd, zkne);
+
+    if (a->rnum > 0xA) {
+        return false;
+    }
+
+    TCGv rnum = tcg_const_tl(a->rnum);
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    gen_helper_aes64ks1i(dest, src1, rnum);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    tcg_temp_free(rnum);
+    return true;
+}
+
+static bool trans_aes64im(DisasContext *ctx, arg_aes64im *a)
+{
+    REQUIRE_ZKND(ctx);
+
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+
+    gen_helper_aes64im(dest, src1);
+    gen_set_gpr(ctx, a->rd, dest);
+
+    return true;
+}