| Message ID | 20220228144810.7284-10-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | support subsets of scalar crypto extension | expand |
On 2/28/22 04:48, Weiwei Li wrote: > +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \ > +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \ > +{ \ > + TCGv_i64 t0 = tcg_temp_new_i64(); \ > + TCGv_i64 t1 = tcg_temp_new_i64(); \ > + TCGv_i64 t2 = tcg_temp_new_i64(); \ > + \ > + tcg_gen_concat_tl_i64(t0, src1, src2); \ > + tcg_gen_##OP##_i64(t1, t0, NUM1); \ > + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \ The bug here is tcg_const_tl instead of tcg_constant_tl, which leaks a temporary. It's not the best option for zero-extension, though, as we don't optimize a deposit of zero like this (we probably should, but, hey). Better would be tcg_gen_extu_tl_i64(t2, src1); tcg_gen_ext32u_i64(t2, t2); Note that the first operation will *not* extend if TARGET_RISCV64, since it doesn't actually change type. The second operation will be optimized away if TARGET_RISCV32, since the zero-extend has already happened. BTW, it would be better to not use a large macro for this, and in the previous patch. Passing in parameters to a helper function would be easier to read and debug. r~
在 2022/3/1 上午3:38, Richard Henderson 写道: > On 2/28/22 04:48, Weiwei Li wrote: >> +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \ >> +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \ >> +{ \ >> + TCGv_i64 t0 = tcg_temp_new_i64(); \ >> + TCGv_i64 t1 = tcg_temp_new_i64(); \ >> + TCGv_i64 t2 = tcg_temp_new_i64(); \ >> + \ >> + tcg_gen_concat_tl_i64(t0, src1, src2); \ >> + tcg_gen_##OP##_i64(t1, t0, NUM1); \ >> + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \ > > The bug here is tcg_const_tl instead of tcg_constant_tl, which leaks a > temporary. > > It's not the best option for zero-extension, though, as we don't > optimize a deposit of zero like this (we probably should, but, hey). > > Better would be > > tcg_gen_extu_tl_i64(t2, src1); > tcg_gen_ext32u_i64(t2, t2); > > Note that the first operation will *not* extend if TARGET_RISCV64, > since it doesn't actually change type. The second operation will be > optimized away if TARGET_RISCV32, since the zero-extend has already > happened. > OK. I'll update this. > BTW, it would be better to not use a large macro for this, and in the > previous patch. Passing in parameters to a helper function would be > easier to read and debug. > OK I'll try to replace this as parameters to a function. Regards, Weiwei Li > > r~
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index db28ecdd2b..02a0c71890 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -862,3 +862,9 @@ sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2 sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2 sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2 sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2 +sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r +sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r +sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r +sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r +sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r +sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r diff --git a/target/riscv/insn_trans/trans_rvk.c.inc b/target/riscv/insn_trans/trans_rvk.c.inc index 02a3261675..f1dccc13c8 100644 --- a/target/riscv/insn_trans/trans_rvk.c.inc +++ b/target/riscv/insn_trans/trans_rvk.c.inc @@ -149,3 +149,66 @@ GEN_SHA256(sha256sig0, shri, 7, 18, 3) GEN_SHA256(sha256sig1, shri, 17, 19, 10) GEN_SHA256(sha256sum0, rotri, 2, 13, 22) GEN_SHA256(sha256sum1, rotri, 6, 11, 25) + +#define GEN_SHA512_RV32(NAME, OP1, NUM1, OP2, NUM2, NUM3) \ +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \ +{ \ + TCGv_i64 t0 = tcg_temp_new_i64(); \ + TCGv_i64 t1 = tcg_temp_new_i64(); \ + TCGv_i64 t2 = tcg_temp_new_i64(); \ + \ + tcg_gen_concat_tl_i64(t0, src1, src2); \ + tcg_gen_##OP1##_i64(t1, t0, NUM1); \ + tcg_gen_##OP2##_i64(t2, t0, NUM2); \ + tcg_gen_xor_i64(t1, t1, t2); \ + tcg_gen_rotri_i64(t2, t0, NUM3); \ + tcg_gen_xor_i64(t1, t1, t2); \ + tcg_gen_trunc_i64_tl(dest, t1); \ + \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ +} \ +\ +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ +{ \ + REQUIRE_32BIT(ctx); \ + REQUIRE_ZKNH(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \ +} + +GEN_SHA512_RV32(sha512sum0r, rotli, 25, rotli, 30, 28) +GEN_SHA512_RV32(sha512sum1r, rotli, 23, rotri, 14, 18) +GEN_SHA512_RV32(sha512sig0l, rotri, 1, rotri, 7, 8) +GEN_SHA512_RV32(sha512sig1l, rotli, 3, rotri, 6, 19) + +#define GEN_SHA512H_RV32(NAME, OP, NUM1, NUM2, NUM3) \ +static void gen_##NAME(TCGv dest, TCGv src1, TCGv src2) \ +{ \ + TCGv_i64 t0 = tcg_temp_new_i64(); \ + TCGv_i64 t1 = tcg_temp_new_i64(); \ + TCGv_i64 t2 = tcg_temp_new_i64(); \ + \ + tcg_gen_concat_tl_i64(t0, src1, src2); \ + tcg_gen_##OP##_i64(t1, t0, NUM1); \ + tcg_gen_concat_tl_i64(t2, src1, tcg_const_tl(0)); \ + tcg_gen_shri_i64(t2, t2, NUM2); \ + tcg_gen_xor_i64(t1, t1, t2); \ + tcg_gen_rotri_i64(t2, t0, NUM3); \ + tcg_gen_xor_i64(t1, t1, t2); \ + tcg_gen_trunc_i64_tl(dest, t1); \ + \ + tcg_temp_free_i64(t0); \ + tcg_temp_free_i64(t1); \ + tcg_temp_free_i64(t2); \ +} \ +\ +static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \ +{ \ + REQUIRE_32BIT(ctx); \ + REQUIRE_ZKNH(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_##NAME, NULL); \ +} + +GEN_SHA512H_RV32(sha512sig0h, rotri, 1, 7, 8) +GEN_SHA512H_RV32(sha512sig1h, rotli, 3, 6, 19)