| Message ID | 20220303172041.1915037-6-matheus.ferst@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | tests/tcg/ppc64le: fix the build of TCG tests with Clang | expand |
On 3/3/22 07:20, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst <matheus.ferst@eldorado.org.br> > > LLVM/Clang doesn't know the VSX registers when compiling with > -mabi=elfv1. Use only registers >= 32 and list them with their Altivec > name. > > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> This description isn't quite right. The change to the m[tf]vsr insns is a generic bug fix, and not related to Clang. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 03/03/2022 16:30, Richard Henderson wrote: > On 3/3/22 07:20, matheus.ferst@eldorado.org.br wrote: >> From: Matheus Ferst <matheus.ferst@eldorado.org.br> >> >> LLVM/Clang doesn't know the VSX registers when compiling with >> -mabi=elfv1. Use only registers >= 32 and list them with their Altivec >> name. >> >> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> > > This description isn't quite right. The change to the m[tf]vsr insns is > a generic bug > fix, and not related to Clang. > I'm not sure if I understood. I'm targeting the Clang problem with this patch, is something else being fixed by this change? AFAICT, the old "mtvsrd 0, %2" and "mfvsrd %0, 0" were correct, I'm just changing from VSR 0 to VSR 32 to allow the clobber with Clang, but GCC doesn't seem to have this limitation with ELFv1. Thanks, Matheus K. Ferst Instituto de Pesquisas ELDORADO <http://www.eldorado.org.br/> Analista de Software Aviso Legal - Disclaimer <https://www.eldorado.org.br/disclaimer.html>
On 3/3/22 10:53, Matheus K. Ferst wrote: > On 03/03/2022 16:30, Richard Henderson wrote: >> On 3/3/22 07:20, matheus.ferst@eldorado.org.br wrote: >>> From: Matheus Ferst <matheus.ferst@eldorado.org.br> >>> >>> LLVM/Clang doesn't know the VSX registers when compiling with >>> -mabi=elfv1. Use only registers >= 32 and list them with their Altivec >>> name. >>> >>> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> >> >> This description isn't quite right. The change to the m[tf]vsr insns is a generic bug >> fix, and not related to Clang. >> > > I'm not sure if I understood. I'm targeting the Clang problem with this patch, is > something else being fixed by this change? > AFAICT, the old "mtvsrd 0, %2" and "mfvsrd %0, 0" were correct, I'm just changing from VSR > 0 to VSR 32 to allow the clobber with Clang, but GCC doesn't seem to have this limitation > with ELFv1. Oh, whoops, I mis-read the patch. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/non_signalling_xscv.c index 91e25cad46..836df71ef0 100644 --- a/tests/tcg/ppc64le/non_signalling_xscv.c +++ b/tests/tcg/ppc64le/non_signalling_xscv.c @@ -6,16 +6,16 @@ #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \ do { \ uint64_t th, tl, bh = B_HI, bl = B_LO; \ - asm("mtvsrd 0, %2\n\t" \ - "mtvsrd 1, %3\n\t" \ - "xxmrghd 0, 0, 1\n\t" \ - INSN " 0, 0\n\t" \ - "mfvsrd %0, 0\n\t" \ - "xxswapd 0, 0\n\t" \ - "mfvsrd %1, 0\n\t" \ + asm("mtvsrd 32, %2\n\t" \ + "mtvsrd 33, %3\n\t" \ + "xxmrghd 32, 32, 33\n\t" \ + INSN " 32, 32\n\t" \ + "mfvsrd %0, 32\n\t" \ + "xxswapd 32, 32\n\t" \ + "mfvsrd %1, 32\n\t" \ : "=r" (th), "=r" (tl) \ : "r" (bh), "r" (bl) \ - : "vs0", "vs1"); \ + : "v0", "v1"); \ printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") = 0x%016" PRIx64 \ "%016" PRIx64 "\n", bh, bl, th, tl); \ assert(th == T_HI && tl == T_LO); \