Message ID | 20220325111851.718966-1-matheus.ferst@eldorado.org.br (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [for-7.0] target/ppc: fix helper_xvmadd* argument order | expand |
On 3/25/22 08:18, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst <matheus.ferst@eldorado.org.br> > > When the xsmadd* insns were moved to decodetree, the helper arguments > were reordered to better match the PowerISA description. The same macro > is used to declare xvmadd* helpers, but the translation macro of these > insns was not changed accordingly. > > Reported-by: Víctor Colombo <victor.colombo@eldorado.org.br> > Fixes: e4318ab2e423 ("target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree") > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > target/ppc/translate/vsx-impl.c.inc | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc > index e67fbf2bb8..d1f6333314 100644 > --- a/target/ppc/translate/vsx-impl.c.inc > +++ b/target/ppc/translate/vsx-impl.c.inc > @@ -1324,31 +1324,31 @@ TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO) > #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ > static void gen_##name(DisasContext *ctx) \ > { \ > - TCGv_ptr xt, xa, b, c; \ > + TCGv_ptr xt, s1, s2, s3; \ > if (unlikely(!ctx->vsx_enabled)) { \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > xt = gen_vsr_ptr(xT(ctx->opcode)); \ > - xa = gen_vsr_ptr(xA(ctx->opcode)); \ > + s1 = gen_vsr_ptr(xA(ctx->opcode)); \ > if (ctx->opcode & PPC_BIT32(25)) { \ > /* \ > * AxT + B \ > */ \ > - b = gen_vsr_ptr(xT(ctx->opcode)); \ > - c = gen_vsr_ptr(xB(ctx->opcode)); \ > + s2 = gen_vsr_ptr(xB(ctx->opcode)); \ > + s3 = gen_vsr_ptr(xT(ctx->opcode)); \ > } else { \ > /* \ > * AxB + T \ > */ \ > - b = gen_vsr_ptr(xB(ctx->opcode)); \ > - c = gen_vsr_ptr(xT(ctx->opcode)); \ > + s2 = gen_vsr_ptr(xT(ctx->opcode)); \ > + s3 = gen_vsr_ptr(xB(ctx->opcode)); \ > } \ > - gen_helper_##name(cpu_env, xt, xa, b, c); \ > + gen_helper_##name(cpu_env, xt, s1, s2, s3); \ > tcg_temp_free_ptr(xt); \ > - tcg_temp_free_ptr(xa); \ > - tcg_temp_free_ptr(b); \ > - tcg_temp_free_ptr(c); \ > + tcg_temp_free_ptr(s1); \ > + tcg_temp_free_ptr(s2); \ > + tcg_temp_free_ptr(s3); \ > } > > GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
On 25/03/2022 08:18, matheus.ferst@eldorado.org.br wrote: > From: Matheus Ferst <matheus.ferst@eldorado.org.br> > > When the xsmadd* insns were moved to decodetree, the helper arguments > were reordered to better match the PowerISA description. The same macro > is used to declare xvmadd* helpers, but the translation macro of these > insns was not changed accordingly. > > Reported-by: Víctor Colombo <victor.colombo@eldorado.org.br> > Fixes: e4318ab2e423 ("target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree") > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> > --- Tested-by: Víctor Colombo <victor.colombo@eldorado.org.br> > target/ppc/translate/vsx-impl.c.inc | 20 ++++++++++---------- > 1 file changed, 10 insertions(+), 10 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc > index e67fbf2bb8..d1f6333314 100644 > --- a/target/ppc/translate/vsx-impl.c.inc > +++ b/target/ppc/translate/vsx-impl.c.inc > @@ -1324,31 +1324,31 @@ TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO) > #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ > static void gen_##name(DisasContext *ctx) \ > { \ > - TCGv_ptr xt, xa, b, c; \ > + TCGv_ptr xt, s1, s2, s3; \ > if (unlikely(!ctx->vsx_enabled)) { \ > gen_exception(ctx, POWERPC_EXCP_VSXU); \ > return; \ > } \ > xt = gen_vsr_ptr(xT(ctx->opcode)); \ > - xa = gen_vsr_ptr(xA(ctx->opcode)); \ > + s1 = gen_vsr_ptr(xA(ctx->opcode)); \ > if (ctx->opcode & PPC_BIT32(25)) { \ > /* \ > * AxT + B \ > */ \ > - b = gen_vsr_ptr(xT(ctx->opcode)); \ > - c = gen_vsr_ptr(xB(ctx->opcode)); \ > + s2 = gen_vsr_ptr(xB(ctx->opcode)); \ > + s3 = gen_vsr_ptr(xT(ctx->opcode)); \ > } else { \ > /* \ > * AxB + T \ > */ \ > - b = gen_vsr_ptr(xB(ctx->opcode)); \ > - c = gen_vsr_ptr(xT(ctx->opcode)); \ > + s2 = gen_vsr_ptr(xT(ctx->opcode)); \ > + s3 = gen_vsr_ptr(xB(ctx->opcode)); \ > } \ > - gen_helper_##name(cpu_env, xt, xa, b, c); \ > + gen_helper_##name(cpu_env, xt, s1, s2, s3); \ > tcg_temp_free_ptr(xt); \ > - tcg_temp_free_ptr(xa); \ > - tcg_temp_free_ptr(b); \ > - tcg_temp_free_ptr(c); \ > + tcg_temp_free_ptr(s1); \ > + tcg_temp_free_ptr(s2); \ > + tcg_temp_free_ptr(s3); \ > } > > GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index e67fbf2bb8..d1f6333314 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1324,31 +1324,31 @@ TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO) #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ static void gen_##name(DisasContext *ctx) \ { \ - TCGv_ptr xt, xa, b, c; \ + TCGv_ptr xt, s1, s2, s3; \ if (unlikely(!ctx->vsx_enabled)) { \ gen_exception(ctx, POWERPC_EXCP_VSXU); \ return; \ } \ xt = gen_vsr_ptr(xT(ctx->opcode)); \ - xa = gen_vsr_ptr(xA(ctx->opcode)); \ + s1 = gen_vsr_ptr(xA(ctx->opcode)); \ if (ctx->opcode & PPC_BIT32(25)) { \ /* \ * AxT + B \ */ \ - b = gen_vsr_ptr(xT(ctx->opcode)); \ - c = gen_vsr_ptr(xB(ctx->opcode)); \ + s2 = gen_vsr_ptr(xB(ctx->opcode)); \ + s3 = gen_vsr_ptr(xT(ctx->opcode)); \ } else { \ /* \ * AxB + T \ */ \ - b = gen_vsr_ptr(xB(ctx->opcode)); \ - c = gen_vsr_ptr(xT(ctx->opcode)); \ + s2 = gen_vsr_ptr(xT(ctx->opcode)); \ + s3 = gen_vsr_ptr(xB(ctx->opcode)); \ } \ - gen_helper_##name(cpu_env, xt, xa, b, c); \ + gen_helper_##name(cpu_env, xt, s1, s2, s3); \ tcg_temp_free_ptr(xt); \ - tcg_temp_free_ptr(xa); \ - tcg_temp_free_ptr(b); \ - tcg_temp_free_ptr(c); \ + tcg_temp_free_ptr(s1); \ + tcg_temp_free_ptr(s2); \ + tcg_temp_free_ptr(s3); \ } GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)