| Message ID | 20220330021316.18223-1-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RESEND] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 | expand |
On Wed, Mar 30, 2022 at 12:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW, > EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' > > So the start byte for vstart != 0 should take sew into account > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/vector_helper.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 1d4982ef7f..b5fbdabbb1 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) > /* Vector Whole Register Move */ > void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) > { > - /* EEW = 8 */ > + /* EEW = SEW */ > uint32_t maxsz = simd_maxsz(desc); > - uint32_t i = env->vstart; > + uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); > + uint32_t startb = env->vstart * sewb; > + uint32_t i = startb; > > memcpy((uint8_t *)vd + H1(i), > (uint8_t *)vs2 + H1(i), > - maxsz - env->vstart); > + maxsz - startb); > > env->vstart = 0; > } > -- > 2.17.1 > >
On Wed, Mar 30, 2022 at 12:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW, > EMUL = NREG, effective length evl= EMUL * VLEN/SEW.' > > So the start byte for vstart != 0 should take sew into account > > Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> > Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/vector_helper.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index 1d4982ef7f..b5fbdabbb1 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) > /* Vector Whole Register Move */ > void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) > { > - /* EEW = 8 */ > + /* EEW = SEW */ > uint32_t maxsz = simd_maxsz(desc); > - uint32_t i = env->vstart; > + uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); > + uint32_t startb = env->vstart * sewb; > + uint32_t i = startb; > > memcpy((uint8_t *)vd + H1(i), > (uint8_t *)vs2 + H1(i), > - maxsz - env->vstart); > + maxsz - startb); > > env->vstart = 0; > } > -- > 2.17.1 > >
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 1d4982ef7f..b5fbdabbb1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) /* Vector Whole Register Move */ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) { - /* EEW = 8 */ + /* EEW = SEW */ uint32_t maxsz = simd_maxsz(desc); - uint32_t i = env->vstart; + uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t startb = env->vstart * sewb; + uint32_t i = startb; memcpy((uint8_t *)vd + H1(i), (uint8_t *)vs2 + H1(i), - maxsz - env->vstart); + maxsz - startb); env->vstart = 0; }