| Message ID | 20220426124259.44087-1-damien.hedde@greensocs.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Disable cryptographic instructions when neon is disabled | expand |
On 4/26/22 05:42, Damien Hedde wrote: > @@ -1587,6 +1587,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > unset_feature(env, ARM_FEATURE_NEON); > > t = cpu->isar.id_aa64isar0; > + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); > + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); > + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); > t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); > cpu->isar.id_aa64isar0 = t; Missing SHA3, SM3, SM4. Otherwise, good catch, thanks. r~
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e3f8215203..e789d18851 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1587,6 +1587,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) unset_feature(env, ARM_FEATURE_NEON); t = cpu->isar.id_aa64isar0; + t = FIELD_DP64(t, ID_AA64ISAR0, AES, 0); + t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); + t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); t = FIELD_DP64(t, ID_AA64ISAR0, DP, 0); cpu->isar.id_aa64isar0 = t; @@ -1601,6 +1604,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) cpu->isar.id_aa64pfr0 = t; u = cpu->isar.id_isar5; + u = FIELD_DP32(u, ID_ISAR5, AES, 0); + u = FIELD_DP32(u, ID_ISAR5, SHA1, 0); + u = FIELD_DP32(u, ID_ISAR5, SHA2, 0); u = FIELD_DP32(u, ID_ISAR5, RDM, 0); u = FIELD_DP32(u, ID_ISAR5, VCMA, 0); cpu->isar.id_isar5 = u;
As of now, cryptographic instructions ISAR fields are never cleared so we can end up with a cpu with cryptographic instructions but no floating-point/neon instructions which is impossible according to ARM specifications. In QEMU, we have 3 kinds of cpus regarding cryptographic instructions: + no support + cortex-a57/a72: cryptographic extension is optional, floating-point/neon is not. + cortex-a53: crytographic extension is optional as well as floationg-point/neon. But cryptographic requires floating-point/neon support. Therefore we can safely clear the ISAR fields when neon is disabled. Note that other arm cpus seem to follow this. For example cortex-a55 is like cortex-a53 and cortex-a76 is like cortex-57/72. Signed-off-by: Damien Hedde <damien.hedde@greensocs.com> --- Note: if we wanted to provide such configuration, we could have a has_crypto property/feature to represent this. --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)