| Message ID | 20220502225230.237369-1-Jason@zx2c4.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/openrisc: implement shutdown and reset helpers | expand |
On 5/2/22 15:52, Jason A. Donenfeld wrote: > OpenRISC defines various nop instructions in or1k as meaning shutdown or > reset. Implement these in TCG. This has been tested with Linux and > confirmed to work. No, OpenRISC does not define various nop instructions, etc. OpenRISC defines a Power Management Register to handle doze and suspend; there is no specification for shutdown or reset. See https://openrisc.io/architecture r~
On Mon, May 02, 2022 at 04:57:43PM -0700, Richard Henderson wrote: > On 5/2/22 15:52, Jason A. Donenfeld wrote: > > OpenRISC defines various nop instructions in or1k as meaning shutdown or > > reset. Implement these in TCG. This has been tested with Linux and > > confirmed to work. > > No, OpenRISC does not define various nop instructions, etc. > > OpenRISC defines a Power Management Register to handle doze and suspend; there is no > specification for shutdown or reset. > > See https://openrisc.io/architecture Stafford is in the process of documenting/spec'ing the nop stuff. > > > r~ >
On Tue, May 03, 2022 at 10:54:41AM +0200, Jason A. Donenfeld wrote: > On Mon, May 02, 2022 at 04:57:43PM -0700, Richard Henderson wrote: > > On 5/2/22 15:52, Jason A. Donenfeld wrote: > > > OpenRISC defines various nop instructions in or1k as meaning shutdown or > > > reset. Implement these in TCG. This has been tested with Linux and > > > confirmed to work. > > > > No, OpenRISC does not define various nop instructions, etc. > > > > OpenRISC defines a Power Management Register to handle doze and suspend; there is no > > specification for shutdown or reset. > > > > See https://openrisc.io/architecture > > > Stafford is in the process of documenting/spec'ing the nop stuff. Hi Richard, Yes, we had a mail discussion about this with Peter. This being similar to ARM semihosting; enabling these special instructions should be behind the semihosting flag. Something that needs to be done for this patch. If you have concern about this let me now. Mail: - https://www.mail-archive.com/qemu-devel@nongnu.org/msg884560.html Our other simulators implement this, so the compromise is if we document this officially and only implement it behind semihosting peter was OK with it. I haven't started on the documentation yet as I haven't has much time in the last few days though. Or1ksim: - https://github.com/openrisc/or1ksim/blob/79c6f153390127e50259d46a7cc0421aa787d2ed/cpu/or32/insnset.c#L768 sim: - https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=sim/or1k/or1k.c;h=bfab35461bee1457fe8f42179ac6d27f5ad46b96;hb=HEAD -Stafford
On 5/3/22 02:14, Stafford Horne wrote: > Yes, we had a mail discussion about this with Peter. This being similar to ARM > semihosting; enabling these special instructions should be behind the semihosting > flag. Something that needs to be done for this patch. Ah, ok. > Our other simulators implement this, so the compromise is if we document this > officially and only implement it behind semihosting peter was OK with it. > > I haven't started on the documentation yet as I haven't has much time in the > last few days though. > > Or1ksim: > - https://github.com/openrisc/or1ksim/blob/79c6f153390127e50259d46a7cc0421aa787d2ed/cpu/or32/insnset.c#L768 > sim: > - https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=sim/or1k/or1k.c;h=bfab35461bee1457fe8f42179ac6d27f5ad46b96;hb=HEAD Thanks for the pointers. r~
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h index d847814a28..ea3557b3f9 100644 --- a/target/openrisc/helper.h +++ b/target/openrisc/helper.h @@ -64,3 +64,4 @@ DEF_HELPER_FLAGS_1(rfe, 0, void, env) /* sys */ DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl) DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl) +DEF_HELPER_1(nop, void, i32) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 48674231e7..f6249896fb 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" +#include "sysemu/runstate.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -314,3 +315,20 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, /* for rd is passed in, if rd unchanged, just keep it back. */ return rd; } + +void HELPER(nop)(uint32_t arg) +{ +#ifndef CONFIG_USER_ONLY + switch (arg) { + case 0x001: /* NOP_EXIT */ + case 0x00c: /* NOP_EXIT_SILENT */ + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + break; + case 0x00d: /* NOP_RESET */ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + break; + default: + break; + } +#endif +} diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7b8ad43d5f..2e4f3759d4 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -780,6 +780,7 @@ static bool trans_l_sh(DisasContext *dc, arg_store *a) static bool trans_l_nop(DisasContext *dc, arg_l_nop *a) { + gen_helper_nop(cpu_R(dc, a->k)); return true; }
OpenRISC defines various nop instructions in or1k as meaning shutdown or reset. Implement these in TCG. This has been tested with Linux and confirmed to work. Cc: Stafford Horne <shorne@gmail.com> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> --- target/openrisc/helper.h | 1 + target/openrisc/sys_helper.c | 18 ++++++++++++++++++ target/openrisc/translate.c | 1 + 3 files changed, 20 insertions(+)