diff mbox series

[2/2] hw/nvme: support smart AEN

Message ID 20220507072644.263105-3-pizhenwei@bytedance.com (mailing list archive)
State New, archived
Headers show
Series hw/nvme: support smart AEN | expand

Commit Message

zhenwei pi May 7, 2022, 7:26 a.m. UTC 
Support smart AEN on controller side, if the guest side enables this
feature, after injecting smart critical warning, also raise AER.

This can be tested by:
virsh qemu-monitor-command vm '{ "execute": "qom-set", "arguments":
  { "path": "/machine/peripheral/nvme0",
  "property": "smart_critical_warning", "value":1 } }'

Signed-off-by: zhenwei pi <pizhenwei@bytedance.com>
---
 hw/nvme/ctrl.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index 03760ddeae..8236a746c8 100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctrl.c
@@ -6707,6 +6707,7 @@  static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
     NvmeIdCtrl *id = &n->id_ctrl;
     uint8_t *pci_conf = pci_dev->config;
     uint64_t cap = ldq_le_p(&n->bar.cap);
+    uint32_t supported_oaes;
 
     id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
     id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
@@ -6716,7 +6717,13 @@  static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
 
     id->cntlid = cpu_to_le16(n->cntlid);
 
-    id->oaes = cpu_to_le32(NVME_OAES_NS_ATTR);
+    supported_oaes = NVME_OAES_SMART_SPARE | NVME_OAES_SMART_TEMPERATURE |
+                     NVME_OAES_SMART_RELIABILITY |
+                     NVME_OAES_SMART_MEDIA_READ_ONLY |
+                     NVME_OAES_SMART_FAILED_VOLATILE_MEDIA |
+                     NVME_OAES_SMART_PMR_UNRELIABLE |
+                     NVME_OAES_NS_ATTR;
+    id->oaes = cpu_to_le32(supported_oaes);
     id->ctratt |= cpu_to_le32(NVME_CTRATT_ELBAS);
 
     id->rab = 6;