diff mbox series

[01/17] ppc/pnv: rename PnvPHB3.ioda* to PnvPHB3.ioda2*

Message ID 20220507190624.507419-2-danielhb413@gmail.com (mailing list archive)
State New, archived
Headers show
Series powernv: introduce pnv-phb unified devices | expand

Commit Message

Daniel Henrique Barboza May 7, 2022, 7:06 p.m. UTC
We're going to merge all the existing pnv-phb models into a single
pnv-phb model. Users will be able to add phbs by using the same pnv-phb
device, regardless of which powernv machine is being used, and
internally we'll handle which PHB version the device needs to have.

The unified pnv-phb model needs to be usable by the existing pnv_phb3
and pnv_phb4 code base. One way of accomplishing that is to merge
PnvPHB3 and PnvPHB4 into a single PnvPHB struct. To do that we need to
handle the cases where the same attribute might have different
meaning/semantics depending on the version.

One of these attributes is the 'ioda' arrays. This patch renames
PnvPHB3.ioda* arrays to PnvPHB3.ioda2*. The reason why we're calling
'ioda2' is because PnvPHB3 uses IODA version 2.

Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
 hw/pci-host/pnv_phb3.c         | 18 +++++++++---------
 include/hw/pci-host/pnv_phb3.h | 12 ++++++------
 2 files changed, 15 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c
index 3f03467dde..860f8846df 100644
--- a/hw/pci-host/pnv_phb3.c
+++ b/hw/pci-host/pnv_phb3.c
@@ -165,7 +165,7 @@  static void pnv_phb3_check_m64(PnvPHB3 *phb, uint32_t index)
     }
 
     /* Get table entry */
-    m64 = phb->ioda_M64BT[index];
+    m64 = phb->ioda2_M64BT[index];
 
     if (!(m64 & IODA2_M64BT_ENABLE)) {
         return;
@@ -215,7 +215,7 @@  static void pnv_phb3_lxivt_write(PnvPHB3 *phb, unsigned idx, uint64_t val)
 {
     uint8_t server, prio;
 
-    phb->ioda_LXIVT[idx] = val & (IODA2_LXIVT_SERVER |
+    phb->ioda2_LXIVT[idx] = val & (IODA2_LXIVT_SERVER |
                                   IODA2_LXIVT_PRIORITY |
                                   IODA2_LXIVT_NODE_ID);
     server = GETFIELD(IODA2_LXIVT_SERVER, val);
@@ -241,11 +241,11 @@  static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb,
 
     switch (table) {
     case IODA2_TBL_LIST:
-        tptr = phb->ioda_LIST;
+        tptr = phb->ioda2_LIST;
         mask = 7;
         break;
     case IODA2_TBL_LXIVT:
-        tptr = phb->ioda_LXIVT;
+        tptr = phb->ioda2_LXIVT;
         mask = 7;
         break;
     case IODA2_TBL_IVC_CAM:
@@ -263,7 +263,7 @@  static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb,
         mask = 255;
         break;
     case IODA2_TBL_TVT:
-        tptr = phb->ioda_TVT;
+        tptr = phb->ioda2_TVT;
         mask = 511;
         break;
     case IODA2_TBL_TCAM:
@@ -271,15 +271,15 @@  static uint64_t *pnv_phb3_ioda_access(PnvPHB3 *phb,
         mask = 63;
         break;
     case IODA2_TBL_M64BT:
-        tptr = phb->ioda_M64BT;
+        tptr = phb->ioda2_M64BT;
         mask = 15;
         break;
     case IODA2_TBL_M32DT:
-        tptr = phb->ioda_MDT;
+        tptr = phb->ioda2_MDT;
         mask = 255;
         break;
     case IODA2_TBL_PEEV:
-        tptr = phb->ioda_PEEV;
+        tptr = phb->ioda2_PEEV;
         mask = 3;
         break;
     default:
@@ -869,7 +869,7 @@  static IOMMUTLBEntry pnv_phb3_translate_iommu(IOMMUMemoryRegion *iommu,
         }
         /* Choose TVE XXX Use PHB3 Control Register */
         tve_sel = (addr >> 59) & 1;
-        tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel];
+        tve = ds->phb->ioda2_TVT[ds->pe_num * 2 + tve_sel];
         pnv_phb3_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret);
         break;
     case 01:
diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h
index af6ec83cf6..73da31fbd2 100644
--- a/include/hw/pci-host/pnv_phb3.h
+++ b/include/hw/pci-host/pnv_phb3.h
@@ -141,12 +141,12 @@  struct PnvPHB3 {
     MemoryRegion pci_mmio;
     MemoryRegion pci_io;
 
-    uint64_t ioda_LIST[8];
-    uint64_t ioda_LXIVT[8];
-    uint64_t ioda_TVT[512];
-    uint64_t ioda_M64BT[16];
-    uint64_t ioda_MDT[256];
-    uint64_t ioda_PEEV[4];
+    uint64_t ioda2_LIST[8];
+    uint64_t ioda2_LXIVT[8];
+    uint64_t ioda2_TVT[512];
+    uint64_t ioda2_M64BT[16];
+    uint64_t ioda2_MDT[256];
+    uint64_t ioda2_PEEV[4];
 
     uint32_t total_irq;
     ICSState lsis;