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([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:55 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 7/8] target/riscv: Force disable extensions if priv spec version does not match Date: Wed, 11 May 2022 20:15:27 +0530 Message-Id: <20220511144528.393530-8-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220511144528.393530-1-apatel@ventanamicro.com> References: <20220511144528.393530-1-apatel@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the device tree") Signed-off-by: Anup Patel Reviewed-by: Atish Patra --- target/riscv/cpu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f3b61dfd63..25a4ba3e22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -541,6 +541,40 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) set_priv_version(env, priv_version); } + /* Force disable extensions if priv spec version does not match */ + if (env->priv_ver < PRIV_VERSION_1_12_0) { + cpu->cfg.ext_h = false; + cpu->cfg.ext_v = false; + cpu->cfg.ext_zfh = false; + cpu->cfg.ext_zfhmin = false; + cpu->cfg.ext_zfinx = false; + cpu->cfg.ext_zhinx = false; + cpu->cfg.ext_zhinxmin = false; + cpu->cfg.ext_zdinx = false; + cpu->cfg.ext_zba = false; + cpu->cfg.ext_zbb = false; + cpu->cfg.ext_zbc = false; + cpu->cfg.ext_zbkb = false; + cpu->cfg.ext_zbkc = false; + cpu->cfg.ext_zbkx = false; + cpu->cfg.ext_zbs = false; + cpu->cfg.ext_zk = false; + cpu->cfg.ext_zkn = false; + cpu->cfg.ext_zknd = false; + cpu->cfg.ext_zkne = false; + cpu->cfg.ext_zknh = false; + cpu->cfg.ext_zkr = false; + cpu->cfg.ext_zks = false; + cpu->cfg.ext_zksed = false; + cpu->cfg.ext_zksh = false; + cpu->cfg.ext_zkt = false; + cpu->cfg.ext_zve32f = false; + cpu->cfg.ext_zve64f = false; + cpu->cfg.ext_svinval = false; + cpu->cfg.ext_svnapot = false; + cpu->cfg.ext_svpbmt = false; + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); }