From patchwork Wed May 11 21:59:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12846680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A8FC433F5 for ; Wed, 11 May 2022 22:14:49 +0000 (UTC) Received: from localhost ([::1]:43834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noubY-0007oG-K6 for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 18:14:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nouNX-0004dq-VA for qemu-devel@nongnu.org; Wed, 11 May 2022 18:00:19 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:34607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nouNU-0006ex-So for qemu-devel@nongnu.org; Wed, 11 May 2022 18:00:19 -0400 Received: by mail-pl1-x631.google.com with SMTP id n8so3164942plh.1 for ; Wed, 11 May 2022 15:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Dq3AsKzhmTYW0tA0YoLO/eJ29e5Y/pkFqc/1LVLFraE=; b=luPPOT4miCVo1teeSOsF7DShd10QmT0Q/pEYTDqyZvZZbcXHSvMKoE8hu7mfkshCpN PxcN1D2lUcMudG5OFg5gsBygRzGCYDZHB5SUTGYpdm4Yh9tA8hLVFvbXH7OUck7HRwRL EZD28u1Tcys04AgzHsl+CNFdvPUqaf9J+PWcN+7y40ai7+8hS0hn7amb+TK7xWTh0jPB 01aNdeMeJU0iXQzepzv4lt/d5Fsfj21g9/SwYCP5D/OuRbaBduyU+VTInk6sW+0L4a/+ HSJnzUAsimvAIpgbMAiG9eeWRDnTCILHoUmdi/8/HvPHr/r1xzXtw2eMQSrtJuxceSEs WPpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Dq3AsKzhmTYW0tA0YoLO/eJ29e5Y/pkFqc/1LVLFraE=; b=tRW/y9S3Bo0bTdhtqVAIRfE9CaploiAD1KWwfjGf7Ie8/125QNEvy2OgfIoNnpTlL3 bIpXgVncHC6sx2X3EXxaCiyEE+n/R4SO4g5saNknS0IYwdVNi1i9Lq9pUwikOOI9+l91 ZxLSqHwNnOws3kLTnGuHqz9LEzrQgEwRMRoQNv6AzpZFuEDpdE3od4VRWWunHn/2Kv5G P6HGvoJUrf8h09ZwDr6qVNM3Am7tfx9WLnAIihidlMNo/1PclMnJKZLT9XJXrO0anc3H O2LqEtnGvzK/FOJir0DxxsYi24u7eQ2FCnBZgG7RZwkAP1QNus7NdDYBbNfwGga9Hxhm Y+sw== X-Gm-Message-State: AOAM531npV67YaRatj+MYAAPEy1T8i4Fv+tH3z1C2qFXejfehh3ToIe9 fSaywkfWFANE7+AQMZdSNCMI+w== X-Google-Smtp-Source: ABdhPJxkHS5qoqp9G4CK+a3stcKbybihmBdaOg2d4osf7WxNeItfeZXaO9Mz1wVrCxEahOO7UvpLbA== X-Received: by 2002:a17:90a:e7d2:b0:1dc:e6c6:604b with SMTP id kb18-20020a17090ae7d200b001dce6c6604bmr7447165pjb.183.1652306416147; Wed, 11 May 2022 15:00:16 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id r23-20020a62e417000000b0050dc762816asm2261303pfh.68.2022.05.11.15.00.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 15:00:15 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Bin Meng , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 05/12] target/riscv: Implement mcountinhibit CSR Date: Wed, 11 May 2022 14:59:49 -0700 Message-Id: <20220511215956.2351243-6-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220511215956.2351243-1-atishp@rivosinc.com> References: <20220511215956.2351243-1-atishp@rivosinc.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Atish Patra As per the privilege specification v1.11, mcountinhibit allows to start/stop a pmu counter selectively. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 4 ++++ target/riscv/csr.c | 25 +++++++++++++++++++++++++ target/riscv/machine.c | 1 + 4 files changed, 32 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7cbcd8d62fc1..45ac0f2d2614 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -269,6 +269,8 @@ struct CPUArchState { target_ulong scounteren; target_ulong mcounteren; + target_ulong mcountinhibit; + target_ulong sscratch; target_ulong mscratch; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20d064e..b3f7fa713000 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -367,6 +367,10 @@ #define CSR_MHPMCOUNTER29 0xb1d #define CSR_MHPMCOUNTER30 0xb1e #define CSR_MHPMCOUNTER31 0xb1f + +/* Machine counter-inhibit register */ +#define CSR_MCOUNTINHIBIT 0x320 + #define CSR_MHPMEVENT3 0x323 #define CSR_MHPMEVENT4 0x324 #define CSR_MHPMEVENT5 0x325 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7e14f7685fb9..ea1cde68610c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1475,6 +1475,28 @@ static RISCVException write_mtvec(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } +static RISCVException read_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong *val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val = env->mcountinhibit; + return RISCV_EXCP_NONE; +} + +static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (env->priv_ver < PRIV_VERSION_1_11_0) { + return RISCV_EXCP_ILLEGAL_INST; + } + + env->mcountinhibit = val; + return RISCV_EXCP_NONE; +} + static RISCVException read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val) { @@ -3741,6 +3763,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { [CSR_MHPMCOUNTER30] = { "mhpmcounter30", mctr, read_zero }, [CSR_MHPMCOUNTER31] = { "mhpmcounter31", mctr, read_zero }, + [CSR_MCOUNTINHIBIT] = { "mcountinhibit", any, read_mcountinhibit, + write_mcountinhibit }, + [CSR_MHPMEVENT3] = { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] = { "mhpmevent4", any, read_zero }, [CSR_MHPMEVENT5] = { "mhpmevent5", any, read_zero }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 2a437b29a1ce..87cd55bfd3a7 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -330,6 +330,7 @@ const VMStateDescription vmstate_riscv_cpu = { VMSTATE_UINTTL(env.siselect, RISCVCPU), VMSTATE_UINTTL(env.scounteren, RISCVCPU), VMSTATE_UINTTL(env.mcounteren, RISCVCPU), + VMSTATE_UINTTL(env.mcountinhibit, RISCVCPU), VMSTATE_UINTTL(env.sscratch, RISCVCPU), VMSTATE_UINTTL(env.mscratch, RISCVCPU), VMSTATE_UINT64(env.mfromhost, RISCVCPU),