From patchwork Thu May 12 03:17:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 12846965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8DD50C433F5 for ; Thu, 12 May 2022 03:39:03 +0000 (UTC) Received: from localhost ([::1]:37160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nozfK-0002i4-I5 for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 23:39:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39062) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nozMC-0002uj-MS for qemu-devel@nongnu.org; Wed, 11 May 2022 23:19:18 -0400 Received: from mga12.intel.com ([192.55.52.136]:56096) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nozMA-0002s1-Tu for qemu-devel@nongnu.org; Wed, 11 May 2022 23:19:16 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1652325554; x=1683861554; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=geM5ojUJjs9SbmWQaUG9mf3dDvcaeY02c+IzDC9b8/o=; b=Kjg2z70Rstb19GCBxSSk0hwLmKgZ7WEjLRLmfiDt8t3ISQvzAYOcFiyE 0JqKZo+NoKB79xkUTwKv9nVmo7QGtRM2i3l0700CgOMHPTXGPA4WBsvpo RDHqlCHiahQenf5oczuYOBAm9pVLgK/l6Lrb3BIQ1nOwXwSwM3Ugto1+p nreoxTIurOKejzzsClr5nmwSWPxa9YbxHV+qhKuFLLw2mHrHfjjBaUqpG Wzv9Mjn7O1cBXb603J6I8A4wvWxurbBRS+eDgore6Nr6Y9fukfItvxK0u 8ImUhK4LuupGupfFF9vzvpYnUOOaHPW6BT1SLWVcWIHteUuNQw76svwB9 w==; X-IronPort-AV: E=McAfee;i="6400,9594,10344"; a="249770418" X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="249770418" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 May 2022 20:19:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,218,1647327600"; d="scan'208";a="594455769" Received: from lxy-dell.sh.intel.com ([10.239.159.55]) by orsmga008.jf.intel.com with ESMTP; 11 May 2022 20:19:09 -0700 From: Xiaoyao Li To: Paolo Bonzini , Isaku Yamahata , isaku.yamahata@intel.com, Gerd Hoffmann , =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= , Richard Henderson , "Michael S . Tsirkin" , Marcel Apfelbaum , Cornelia Huck , Marcelo Tosatti , Laszlo Ersek , Eric Blake Cc: Connor Kuehl , erdemaktas@google.com, kvm@vger.kernel.org, qemu-devel@nongnu.org, seanjc@google.com, xiaoyao.li@intel.com Subject: [RFC PATCH v4 13/36] i386/tdx: Validate TD attributes Date: Thu, 12 May 2022 11:17:40 +0800 Message-Id: <20220512031803.3315890-14-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20220512031803.3315890-1-xiaoyao.li@intel.com> References: <20220512031803.3315890-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Received-SPF: pass client-ip=192.55.52.136; envelope-from=xiaoyao.li@intel.com; helo=mga12.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.998, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Validate TD attributes with tdx_caps that fixed-0 bits must be zero and fixed-1 bits must be set. Besides, sanity check the attribute bits that have not been supported by QEMU yet. e.g., debug bit, it will be allowed in the future when debug TD support lands in QEMU. Signed-off-by: Xiaoyao Li --- target/i386/kvm/tdx.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c index e9c6e6fb396c..9f2cdf640b5c 100644 --- a/target/i386/kvm/tdx.c +++ b/target/i386/kvm/tdx.c @@ -31,6 +31,7 @@ (1ULL << KVM_FEATURE_PV_SCHED_YIELD) | \ (1ULL << KVM_FEATURE_MSI_EXT_DEST_ID)) +#define TDX_TD_ATTRIBUTES_DEBUG BIT_ULL(0) #define TDX_TD_ATTRIBUTES_PKS BIT_ULL(30) #define TDX_TD_ATTRIBUTES_PERFMON BIT_ULL(63) @@ -169,13 +170,32 @@ void tdx_get_supported_cpuid(uint32_t function, uint32_t index, int reg, } } -static void setup_td_guest_attributes(X86CPU *x86cpu) +static int tdx_validate_attributes(TdxGuest *tdx) +{ + if (((tdx->attributes & tdx_caps->attrs_fixed0) | tdx_caps->attrs_fixed1) != + tdx->attributes) { + error_report("Invalid attributes 0x%lx for TDX VM (fixed0 0x%llx, fixed1 0x%llx)", + tdx->attributes, tdx_caps->attrs_fixed0, tdx_caps->attrs_fixed1); + return -EINVAL; + } + + if (tdx->attributes & TDX_TD_ATTRIBUTES_DEBUG) { + error_report("Current QEMU doesn't support attributes.debug[bit 0] for TDX VM"); + return -EINVAL; + } + + return 0; +} + +static int setup_td_guest_attributes(X86CPU *x86cpu) { CPUX86State *env = &x86cpu->env; tdx_guest->attributes |= (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS) ? TDX_TD_ATTRIBUTES_PKS : 0; tdx_guest->attributes |= x86cpu->enable_pmu ? TDX_TD_ATTRIBUTES_PERFMON : 0; + + return tdx_validate_attributes(tdx_guest); } int tdx_pre_create_vcpu(CPUState *cpu) @@ -191,7 +211,10 @@ int tdx_pre_create_vcpu(CPUState *cpu) goto out; } - setup_td_guest_attributes(x86cpu); + r = setup_td_guest_attributes(x86cpu); + if (r) { + goto out; + } memset(&init_vm, 0, sizeof(init_vm)); init_vm.cpuid.nent = kvm_x86_arch_cpuid(env, init_vm.entries, 0);