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[89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:55:01 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Aurelien Jarno , "Michael S. Tsirkin" , Marcel Apfelbaum Subject: [PATCH 5/6] hw/isa/piix4: Factor out SM bus initialization from create() function Date: Fri, 13 May 2022 19:54:44 +0200 Message-Id: <20220513175445.89616-6-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=shentey@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Initialize the SM bus just like is done for piix3 which modernizes the code. Signed-off-by: Bernhard Beschow --- hw/isa/piix4.c | 15 +++------------ hw/mips/malta.c | 7 ++++++- include/hw/southbridge/piix.h | 2 +- 3 files changed, 10 insertions(+), 14 deletions(-) diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 4968c69da9..852e5c4db1 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -301,21 +301,12 @@ static void piix4_register_types(void) type_init(piix4_register_types) -DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus) +PCIDevice *piix4_create(PCIBus *pci_bus) { PCIDevice *pci; - DeviceState *dev; - int devfn = PCI_DEVFN(10, 0); - pci = pci_create_simple_multifunction(pci_bus, devfn, true, + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0), true, TYPE_PIIX4_PCI_DEVICE); - dev = DEVICE(pci); - if (smbus) { - *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0, NULL); - } - - return dev; + return pci; } diff --git a/hw/mips/malta.c b/hw/mips/malta.c index e446b25ad0..d4bd3549d0 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1238,6 +1238,7 @@ void mips_malta_init(MachineState *machine) int be; MaltaState *s; DeviceState *dev; + PCIDevice *piix4; s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA)); sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal); @@ -1399,8 +1400,12 @@ void mips_malta_init(MachineState *machine) empty_slot_init("GT64120", 0, 0x20000000); /* Southbridge */ - dev = piix4_create(pci_bus, &smbus); + piix4 = piix4_create(pci_bus); + dev = DEVICE(piix4); isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0")); + smbus = piix4_pm_init(pci_bus, piix4->devfn + 3, 0x1100, + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0, NULL); /* Interrupt controller */ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq); diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index b768109f30..bea3b44551 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -74,6 +74,6 @@ DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, PIIX3State *piix3_create(PCIBus *pci_bus); -DeviceState *piix4_create(PCIBus *pci_bus, I2CBus **smbus); +PCIDevice *piix4_create(PCIBus *pci_bus); #endif