| Message ID | 20220517111605.1494647-1-its@irrelevant.dk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/nvme: clean up CC register write logic | expand |
On Tue, May 17, 2022 at 01:16:05PM +0200, Klaus Jensen wrote: > From: Klaus Jensen <k.jensen@samsung.com> > > The SRIOV series exposed an issued with how CC register writes are > handled and how CSTS is set in response to that. Specifically, after > applying the SRIOV series, the controller could end up in a state with > CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to > expect CSTS.RDY to transition to '1' but timing out. > > Clean this up. > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com> > --- > > Note, this applies on top of nvme-next with v8 of Lukasz's sriov series. > > hw/nvme/ctrl.c | 35 +++++++++++------------------------ > 1 file changed, 11 insertions(+), 24 deletions(-) > > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > index 658584d417fe..47d971b2404c 100644 > --- a/hw/nvme/ctrl.c > +++ b/hw/nvme/ctrl.c > @@ -6190,9 +6190,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) > > if (pci_is_vf(pci_dev)) { > sctrl = nvme_sctrl(n); > + > stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED); > - } else { > - stl_le_p(&n->bar.csts, 0); Are you sure the registers do not need to be cleared for a reset type that does not involve a CC register i.e. FLR? Will these registers be zeroed out elsewhere during FLR? > } > } > > @@ -6405,20 +6404,21 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, > nvme_irq_check(n); > break; > case NVME_REG_CC: > + stl_le_p(&n->bar.cc, data); > + > trace_pci_nvme_mmio_cfg(data & 0xffffffff); > > - /* Windows first sends data, then sends enable bit */ > - if (!NVME_CC_EN(data) && !NVME_CC_EN(cc) && > - !NVME_CC_SHN(data) && !NVME_CC_SHN(cc)) > - { > - cc = data; > + if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { > + trace_pci_nvme_mmio_shutdown_set(); > + nvme_ctrl_shutdown(n); > + csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); > + csts |= NVME_CSTS_SHST_COMPLETE; > + } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { > + trace_pci_nvme_mmio_shutdown_cleared(); > + csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); > } > > if (NVME_CC_EN(data) && !NVME_CC_EN(cc)) { > - cc = data; > - > - /* flush CC since nvme_start_ctrl() needs the value */ > - stl_le_p(&n->bar.cc, cc); > if (unlikely(nvme_start_ctrl(n))) { > trace_pci_nvme_err_startfail(); > csts = NVME_CSTS_FAILED; > @@ -6429,22 +6429,9 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, > } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) { > trace_pci_nvme_mmio_stopped(); > nvme_ctrl_reset(n, NVME_RESET_CONTROLLER); > - cc = 0; > csts &= ~NVME_CSTS_READY; > } > > - if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { > - trace_pci_nvme_mmio_shutdown_set(); > - nvme_ctrl_shutdown(n); > - cc = data; > - csts |= NVME_CSTS_SHST_COMPLETE; > - } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { > - trace_pci_nvme_mmio_shutdown_cleared(); > - csts &= ~NVME_CSTS_SHST_COMPLETE; > - cc = data; > - } > - > - stl_le_p(&n->bar.cc, cc); > stl_le_p(&n->bar.csts, csts); > > break; > -- > 2.36.1 >
On May 19 14:11, Lukasz Maniak wrote: > On Tue, May 17, 2022 at 01:16:05PM +0200, Klaus Jensen wrote: > > From: Klaus Jensen <k.jensen@samsung.com> > > > > The SRIOV series exposed an issued with how CC register writes are > > handled and how CSTS is set in response to that. Specifically, after > > applying the SRIOV series, the controller could end up in a state with > > CC.EN set to '1' but with CSTS.RDY cleared to '0', causing drivers to > > expect CSTS.RDY to transition to '1' but timing out. > > > > Clean this up. > > > > Signed-off-by: Klaus Jensen <k.jensen@samsung.com> > > --- > > > > Note, this applies on top of nvme-next with v8 of Lukasz's sriov series. > > > > hw/nvme/ctrl.c | 35 +++++++++++------------------------ > > 1 file changed, 11 insertions(+), 24 deletions(-) > > > > diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c > > index 658584d417fe..47d971b2404c 100644 > > --- a/hw/nvme/ctrl.c > > +++ b/hw/nvme/ctrl.c > > @@ -6190,9 +6190,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) > > > > if (pci_is_vf(pci_dev)) { > > sctrl = nvme_sctrl(n); > > + > > stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED); > > - } else { > > - stl_le_p(&n->bar.csts, 0); > > Are you sure the registers do not need to be cleared for a reset type that > does not involve a CC register i.e. FLR? > Will these registers be zeroed out elsewhere during FLR? > Indeed you are right. Posting a v2.
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 658584d417fe..47d971b2404c 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -6190,9 +6190,8 @@ static void nvme_ctrl_reset(NvmeCtrl *n, NvmeResetType rst) if (pci_is_vf(pci_dev)) { sctrl = nvme_sctrl(n); + stl_le_p(&n->bar.csts, sctrl->scs ? 0 : NVME_CSTS_FAILED); - } else { - stl_le_p(&n->bar.csts, 0); } } @@ -6405,20 +6404,21 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, nvme_irq_check(n); break; case NVME_REG_CC: + stl_le_p(&n->bar.cc, data); + trace_pci_nvme_mmio_cfg(data & 0xffffffff); - /* Windows first sends data, then sends enable bit */ - if (!NVME_CC_EN(data) && !NVME_CC_EN(cc) && - !NVME_CC_SHN(data) && !NVME_CC_SHN(cc)) - { - cc = data; + if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { + trace_pci_nvme_mmio_shutdown_set(); + nvme_ctrl_shutdown(n); + csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); + csts |= NVME_CSTS_SHST_COMPLETE; + } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { + trace_pci_nvme_mmio_shutdown_cleared(); + csts &= ~(CSTS_SHST_MASK << CSTS_SHST_SHIFT); } if (NVME_CC_EN(data) && !NVME_CC_EN(cc)) { - cc = data; - - /* flush CC since nvme_start_ctrl() needs the value */ - stl_le_p(&n->bar.cc, cc); if (unlikely(nvme_start_ctrl(n))) { trace_pci_nvme_err_startfail(); csts = NVME_CSTS_FAILED; @@ -6429,22 +6429,9 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offset, uint64_t data, } else if (!NVME_CC_EN(data) && NVME_CC_EN(cc)) { trace_pci_nvme_mmio_stopped(); nvme_ctrl_reset(n, NVME_RESET_CONTROLLER); - cc = 0; csts &= ~NVME_CSTS_READY; } - if (NVME_CC_SHN(data) && !(NVME_CC_SHN(cc))) { - trace_pci_nvme_mmio_shutdown_set(); - nvme_ctrl_shutdown(n); - cc = data; - csts |= NVME_CSTS_SHST_COMPLETE; - } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(cc)) { - trace_pci_nvme_mmio_shutdown_cleared(); - csts &= ~NVME_CSTS_SHST_COMPLETE; - cc = data; - } - - stl_le_p(&n->bar.cc, cc); stl_le_p(&n->bar.csts, csts); break;