| Message ID | 20220523153147.15371-1-frank.chang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [RESEND,v2] target/riscv: Fix typo of mimpid cpu option | expand |
On Tue, May 24, 2022 at 1:36 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > "mimpid" cpu option was mistyped to "mipid". > > Fixes: 9951ba94 ("target/riscv: Support configuarable marchid, mvendorid, mipid CSR values") > Signed-off-by: Frank Chang <frank.chang@sifive.com> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 4 ++-- > target/riscv/cpu.h | 2 +- > target/riscv/csr.c | 8 ++++---- > 3 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6d01569cad..a1f847176e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -37,7 +37,7 @@ > #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ > (QEMU_VERSION_MINOR << 8) | \ > (QEMU_VERSION_MICRO)) > -#define RISCV_CPU_MIPID RISCV_CPU_MARCHID > +#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID > > static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; > > @@ -869,7 +869,7 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), > DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), > - DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), > + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), > > DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), > DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5ff7294c6..44975e3e5a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -408,7 +408,7 @@ struct RISCVCPUConfig { > > uint32_t mvendorid; > uint64_t marchid; > - uint64_t mipid; > + uint64_t mimpid; > > /* Vendor-specific custom extensions */ > bool ext_XVentanaCondOps; > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 4ea7df02c9..0d5bc2f41d 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -674,13 +674,13 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > -static RISCVException read_mipid(CPURISCVState *env, int csrno, > - target_ulong *val) > +static RISCVException read_mimpid(CPURISCVState *env, int csrno, > + target_ulong *val) > { > CPUState *cs = env_cpu(env); > RISCVCPU *cpu = RISCV_CPU(cs); > > - *val = cpu->cfg.mipid; > + *val = cpu->cfg.mimpid; > return RISCV_EXCP_NONE; > } > > @@ -3372,7 +3372,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { > /* Machine Information Registers */ > [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, > [CSR_MARCHID] = { "marchid", any, read_marchid }, > - [CSR_MIMPID] = { "mimpid", any, read_mipid }, > + [CSR_MIMPID] = { "mimpid", any, read_mimpid }, > [CSR_MHARTID] = { "mhartid", any, read_mhartid }, > > [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero, > -- > 2.35.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d01569cad..a1f847176e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -37,7 +37,7 @@ #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ (QEMU_VERSION_MINOR << 8) | \ (QEMU_VERSION_MICRO)) -#define RISCV_CPU_MIPID RISCV_CPU_MARCHID +#define RISCV_CPU_MIMPID RISCV_CPU_MARCHID static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; @@ -869,7 +869,7 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), - DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), + DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5ff7294c6..44975e3e5a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -408,7 +408,7 @@ struct RISCVCPUConfig { uint32_t mvendorid; uint64_t marchid; - uint64_t mipid; + uint64_t mimpid; /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 4ea7df02c9..0d5bc2f41d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -674,13 +674,13 @@ static RISCVException read_marchid(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static RISCVException read_mipid(CPURISCVState *env, int csrno, - target_ulong *val) +static RISCVException read_mimpid(CPURISCVState *env, int csrno, + target_ulong *val) { CPUState *cs = env_cpu(env); RISCVCPU *cpu = RISCV_CPU(cs); - *val = cpu->cfg.mipid; + *val = cpu->cfg.mimpid; return RISCV_EXCP_NONE; } @@ -3372,7 +3372,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Machine Information Registers */ [CSR_MVENDORID] = { "mvendorid", any, read_mvendorid }, [CSR_MARCHID] = { "marchid", any, read_marchid }, - [CSR_MIMPID] = { "mimpid", any, read_mipid }, + [CSR_MIMPID] = { "mimpid", any, read_mimpid }, [CSR_MHARTID] = { "mhartid", any, read_mhartid }, [CSR_MCONFIGPTR] = { "mconfigptr", any, read_zero,