| Message ID | 20220531214917.31668-8-danielhb413@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | powernv: introduce pnv-phb base/proxy devices | expand |
On 31/05/2022 22:49, Daniel Henrique Barboza wrote: > Change the parent type of the PnvPHB4 device to TYPE_PARENT since the > PCI bus is going to be initialized by the PnvPHB parent. Functions that > needs to access the bus via a PnvPHB4 object can do so via the > phb4->phb_base pointer. > > pnv_phb4_pec now creates a PnvPHB object. > > The powernv9 machine class will create PnvPHB devices with version '4'. > powernv10 will create using version '5'. Both are using global machine > properties in their class_init() to do that. > > These changes will benefit us when adding PnvPHB user creatable devices > for powernv9 and powernv10. > > Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> > --- > hw/pci-host/pnv_phb4.c | 29 +++++++++-------------------- > hw/pci-host/pnv_phb4_pec.c | 6 +----- > hw/ppc/pnv.c | 20 +++++++++++++++++++- > include/hw/pci-host/pnv_phb4.h | 5 ++++- > 4 files changed, 33 insertions(+), 27 deletions(-) > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index ae5494fe72..22cf1c2a5e 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -49,7 +49,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, > > static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) > { > - PCIHostState *pci = PCI_HOST_BRIDGE(phb); > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; > uint8_t bus, devfn; > > @@ -145,7 +145,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, > static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, > unsigned size, uint64_t val) > { > - PCIHostState *pci = PCI_HOST_BRIDGE(phb); > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > PCIDevice *pdev; > > if (size != 4) { > @@ -166,7 +166,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, > static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, > unsigned size) > { > - PCIHostState *pci = PCI_HOST_BRIDGE(phb); > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > PCIDevice *pdev; > uint64_t val; > > @@ -1608,16 +1608,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) > pnv_phb4_xscom_realize(phb); > } > > -static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, > - PCIBus *rootbus) > -{ > - PnvPHB4 *phb = PNV_PHB4(host_bridge); > - > - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", > - phb->chip_id, phb->phb_id); > - return phb->bus_path; > -} > - > /* > * Address base trigger mode (POWER10) > * > @@ -1702,19 +1692,18 @@ static Property pnv_phb4_properties[] = { > DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), > DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, > PnvPhb4PecState *), > + DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, > + TYPE_PNV_PHB, PnvPHB *), > DEFINE_PROP_END_OF_LIST(), > }; > > static void pnv_phb4_class_init(ObjectClass *klass, void *data) > { > - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); > DeviceClass *dc = DEVICE_CLASS(klass); > XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); > > - hc->root_bus_path = pnv_phb4_root_bus_path; > dc->realize = pnv_phb4_realize; > device_class_set_props(dc, pnv_phb4_properties); > - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); > dc->user_creatable = false; > > xfc->notify = pnv_phb4_xive_notify; > @@ -1722,7 +1711,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) > > static const TypeInfo pnv_phb4_type_info = { > .name = TYPE_PNV_PHB4, > - .parent = TYPE_PCIE_HOST_BRIDGE, > + .parent = TYPE_DEVICE, > .instance_init = pnv_phb4_instance_init, > .instance_size = sizeof(PnvPHB4), > .class_init = pnv_phb4_class_init, > @@ -1785,11 +1774,11 @@ static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) > PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); > PCIDevice *pci = PCI_DEVICE(dev); > PCIBus *bus = pci_get_bus(pci); > - PnvPHB4 *phb = NULL; > + PnvPHB *phb = NULL; > Error *local_err = NULL; > > - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), > - TYPE_PNV_PHB4); > + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), > + TYPE_PNV_PHB); Same comment here re: accessing bus->qbus directly. > if (!phb) { > error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); > diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c > index 61bc0b503e..888ecbe8f3 100644 > --- a/hw/pci-host/pnv_phb4_pec.c > +++ b/hw/pci-host/pnv_phb4_pec.c > @@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, > int stack_no, > Error **errp) > { > - PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); > - PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); > + PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); > int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); > > object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); > @@ -130,9 +129,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, > if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { > return; > } > - > - /* Add a single Root port if running with defaults */ > - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); > } > > static void pnv_pec_realize(DeviceState *dev, Error **errp) > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 081b6839cc..3b0b230e49 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -688,7 +688,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) > static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) > { > Monitor *mon = opaque; > - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); > + PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); I'm sure this could just be: PnvPHB *phb = PNV_PHB(child); > + PnvPHB4 *phb4; > + > + if (!phb) { > + return 0; > + } > + > + phb4 = (PnvPHB4 *)phb->backend; and you should be able to do: phb4 = PNV_PHB4(phb->backend); My preference for using the QOM macros where possible is that they also include a type check that assert()s if you assign the wrong type of QOM object, which a direct C cast would miss. > if (phb4) { > pnv_phb4_pic_print_info(phb4, mon); > @@ -2164,8 +2171,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); > static const char compat[] = "qemu,powernv9\0ibm,powernv"; > > + static GlobalProperty phb_compat[] = { > + { TYPE_PNV_PHB, "version", "4" }, > + }; > + > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > + > xfc->match_nvt = pnv_match_nvt; > > mc->alias = "powernv"; > @@ -2182,8 +2195,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) > XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); > static const char compat[] = "qemu,powernv10\0ibm,powernv"; > > + static GlobalProperty phb_compat[] = { > + { TYPE_PNV_PHB, "version", "5" }, > + }; > + > mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); > + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > > pmc->compat = compat; > pmc->compat_size = sizeof(compat); > diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h > index 90843ac3a9..f22253358f 100644 > --- a/include/hw/pci-host/pnv_phb4.h > +++ b/include/hw/pci-host/pnv_phb4.h > @@ -18,6 +18,7 @@ > typedef struct PnvPhb4PecState PnvPhb4PecState; > typedef struct PnvPhb4PecStack PnvPhb4PecStack; > typedef struct PnvPHB4 PnvPHB4; > +typedef struct PnvPHB PnvPHB; > typedef struct PnvChip PnvChip; > > /* > @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) > #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) > > struct PnvPHB4 { > - PCIExpressHost parent_obj; > + DeviceState parent; > + > + PnvPHB *phb_base; > > uint32_t chip_id; > uint32_t phb_id; ATB, Mark.
On 31/05/2022 23:49, Daniel Henrique Barboza wrote: > Change the parent type of the PnvPHB4 device to TYPE_PARENT since the s/TYPE_PARENT/TYPE_DEVICE Fred > PCI bus is going to be initialized by the PnvPHB parent. Functions that > needs to access the bus via a PnvPHB4 object can do so via the > phb4->phb_base pointer. > > pnv_phb4_pec now creates a PnvPHB object. > > The powernv9 machine class will create PnvPHB devices with version '4'. > powernv10 will create using version '5'. Both are using global machine > properties in their class_init() to do that. > > These changes will benefit us when adding PnvPHB user creatable devices > for powernv9 and powernv10. > > Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> > --- > hw/pci-host/pnv_phb4.c | 29 +++++++++-------------------- > hw/pci-host/pnv_phb4_pec.c | 6 +----- > hw/ppc/pnv.c | 20 +++++++++++++++++++- > include/hw/pci-host/pnv_phb4.h | 5 ++++- > 4 files changed, 33 insertions(+), 27 deletions(-) > > diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c > index ae5494fe72..22cf1c2a5e 100644 > --- a/hw/pci-host/pnv_phb4.c > +++ b/hw/pci-host/pnv_phb4.c > @@ -49,7 +49,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, > > static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) > { > - PCIHostState *pci = PCI_HOST_BRIDGE(phb); > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; > uint8_t bus, devfn; > > @@ -145,7 +145,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, > static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, > unsigned size, uint64_t val) > { > - PCIHostState *pci = PCI_HOST_BRIDGE(phb); > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > PCIDevice *pdev; > > if (size != 4) { > @@ -166,7 +166,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, > static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, > unsigned size) > { > - PCIHostState *pci = PCI_HOST_BRIDGE(phb); > + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); > PCIDevice *pdev; > uint64_t val; > > @@ -1608,16 +1608,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) > pnv_phb4_xscom_realize(phb); > } > > -static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, > - PCIBus *rootbus) > -{ > - PnvPHB4 *phb = PNV_PHB4(host_bridge); > - > - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", > - phb->chip_id, phb->phb_id); > - return phb->bus_path; > -} > - > /* > * Address base trigger mode (POWER10) > * > @@ -1702,19 +1692,18 @@ static Property pnv_phb4_properties[] = { > DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), > DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, > PnvPhb4PecState *), > + DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, > + TYPE_PNV_PHB, PnvPHB *), > DEFINE_PROP_END_OF_LIST(), > }; > > static void pnv_phb4_class_init(ObjectClass *klass, void *data) > { > - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); > DeviceClass *dc = DEVICE_CLASS(klass); > XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); > > - hc->root_bus_path = pnv_phb4_root_bus_path; > dc->realize = pnv_phb4_realize; > device_class_set_props(dc, pnv_phb4_properties); > - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); > dc->user_creatable = false; > > xfc->notify = pnv_phb4_xive_notify; > @@ -1722,7 +1711,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) > > static const TypeInfo pnv_phb4_type_info = { > .name = TYPE_PNV_PHB4, > - .parent = TYPE_PCIE_HOST_BRIDGE, > + .parent = TYPE_DEVICE, > .instance_init = pnv_phb4_instance_init, > .instance_size = sizeof(PnvPHB4), > .class_init = pnv_phb4_class_init, > @@ -1785,11 +1774,11 @@ static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) > PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); > PCIDevice *pci = PCI_DEVICE(dev); > PCIBus *bus = pci_get_bus(pci); > - PnvPHB4 *phb = NULL; > + PnvPHB *phb = NULL; > Error *local_err = NULL; > > - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), > - TYPE_PNV_PHB4); > + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), > + TYPE_PNV_PHB); > > if (!phb) { > error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); > diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c > index 61bc0b503e..888ecbe8f3 100644 > --- a/hw/pci-host/pnv_phb4_pec.c > +++ b/hw/pci-host/pnv_phb4_pec.c > @@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, > int stack_no, > Error **errp) > { > - PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); > - PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); > + PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); > int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); > > object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); > @@ -130,9 +129,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, > if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { > return; > } > - > - /* Add a single Root port if running with defaults */ > - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); > } > > static void pnv_pec_realize(DeviceState *dev, Error **errp) > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 081b6839cc..3b0b230e49 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -688,7 +688,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) > static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) > { > Monitor *mon = opaque; > - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); > + PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); > + PnvPHB4 *phb4; > + > + if (!phb) { > + return 0; > + } > + > + phb4 = (PnvPHB4 *)phb->backend; > > if (phb4) { > pnv_phb4_pic_print_info(phb4, mon); > @@ -2164,8 +2171,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); > static const char compat[] = "qemu,powernv9\0ibm,powernv"; > > + static GlobalProperty phb_compat[] = { > + { TYPE_PNV_PHB, "version", "4" }, > + }; > + > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > + > xfc->match_nvt = pnv_match_nvt; > > mc->alias = "powernv"; > @@ -2182,8 +2195,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) > XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); > static const char compat[] = "qemu,powernv10\0ibm,powernv"; > > + static GlobalProperty phb_compat[] = { > + { TYPE_PNV_PHB, "version", "5" }, > + }; > + > mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); > + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); > > pmc->compat = compat; > pmc->compat_size = sizeof(compat); > diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h > index 90843ac3a9..f22253358f 100644 > --- a/include/hw/pci-host/pnv_phb4.h > +++ b/include/hw/pci-host/pnv_phb4.h > @@ -18,6 +18,7 @@ > typedef struct PnvPhb4PecState PnvPhb4PecState; > typedef struct PnvPhb4PecStack PnvPhb4PecStack; > typedef struct PnvPHB4 PnvPHB4; > +typedef struct PnvPHB PnvPHB; > typedef struct PnvChip PnvChip; > > /* > @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) > #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) > > struct PnvPHB4 { > - PCIExpressHost parent_obj; > + DeviceState parent; > + > + PnvPHB *phb_base; > > uint32_t chip_id; > uint32_t phb_id;
On 6/2/22 10:02, Mark Cave-Ayland wrote: > On 31/05/2022 22:49, Daniel Henrique Barboza wrote: > >> Change the parent type of the PnvPHB4 device to TYPE_PARENT since the >> PCI bus is going to be initialized by the PnvPHB parent. Functions that >> needs to access the bus via a PnvPHB4 object can do so via the >> phb4->phb_base pointer. >> >> pnv_phb4_pec now creates a PnvPHB object. >> >> The powernv9 machine class will create PnvPHB devices with version '4'. >> powernv10 will create using version '5'. Both are using global machine >> properties in their class_init() to do that. >> >> These changes will benefit us when adding PnvPHB user creatable devices >> for powernv9 and powernv10. >> >> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> >> --- >> hw/pci-host/pnv_phb4.c | 29 +++++++++-------------------- >> hw/pci-host/pnv_phb4_pec.c | 6 +----- >> hw/ppc/pnv.c | 20 +++++++++++++++++++- >> include/hw/pci-host/pnv_phb4.h | 5 ++++- >> 4 files changed, 33 insertions(+), 27 deletions(-) >> >> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c >> index ae5494fe72..22cf1c2a5e 100644 >> --- a/hw/pci-host/pnv_phb4.c >> +++ b/hw/pci-host/pnv_phb4.c >> @@ -49,7 +49,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, >> static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) >> { >> - PCIHostState *pci = PCI_HOST_BRIDGE(phb); >> + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); >> uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; >> uint8_t bus, devfn; >> @@ -145,7 +145,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, >> static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, >> unsigned size, uint64_t val) >> { >> - PCIHostState *pci = PCI_HOST_BRIDGE(phb); >> + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); >> PCIDevice *pdev; >> if (size != 4) { >> @@ -166,7 +166,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, >> static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, >> unsigned size) >> { >> - PCIHostState *pci = PCI_HOST_BRIDGE(phb); >> + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); >> PCIDevice *pdev; >> uint64_t val; >> @@ -1608,16 +1608,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) >> pnv_phb4_xscom_realize(phb); >> } >> -static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, >> - PCIBus *rootbus) >> -{ >> - PnvPHB4 *phb = PNV_PHB4(host_bridge); >> - >> - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", >> - phb->chip_id, phb->phb_id); >> - return phb->bus_path; >> -} >> - >> /* >> * Address base trigger mode (POWER10) >> * >> @@ -1702,19 +1692,18 @@ static Property pnv_phb4_properties[] = { >> DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), >> DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, >> PnvPhb4PecState *), >> + DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, >> + TYPE_PNV_PHB, PnvPHB *), >> DEFINE_PROP_END_OF_LIST(), >> }; >> static void pnv_phb4_class_init(ObjectClass *klass, void *data) >> { >> - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); >> DeviceClass *dc = DEVICE_CLASS(klass); >> XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); >> - hc->root_bus_path = pnv_phb4_root_bus_path; >> dc->realize = pnv_phb4_realize; >> device_class_set_props(dc, pnv_phb4_properties); >> - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); >> dc->user_creatable = false; >> xfc->notify = pnv_phb4_xive_notify; >> @@ -1722,7 +1711,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) >> static const TypeInfo pnv_phb4_type_info = { >> .name = TYPE_PNV_PHB4, >> - .parent = TYPE_PCIE_HOST_BRIDGE, >> + .parent = TYPE_DEVICE, >> .instance_init = pnv_phb4_instance_init, >> .instance_size = sizeof(PnvPHB4), >> .class_init = pnv_phb4_class_init, >> @@ -1785,11 +1774,11 @@ static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) >> PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); >> PCIDevice *pci = PCI_DEVICE(dev); >> PCIBus *bus = pci_get_bus(pci); >> - PnvPHB4 *phb = NULL; >> + PnvPHB *phb = NULL; >> Error *local_err = NULL; >> - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), >> - TYPE_PNV_PHB4); >> + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), >> + TYPE_PNV_PHB); > > Same comment here re: accessing bus->qbus directly. > >> if (!phb) { >> error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); >> diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c >> index 61bc0b503e..888ecbe8f3 100644 >> --- a/hw/pci-host/pnv_phb4_pec.c >> +++ b/hw/pci-host/pnv_phb4_pec.c >> @@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, >> int stack_no, >> Error **errp) >> { >> - PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); >> - PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); >> + PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); >> int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); >> object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); >> @@ -130,9 +129,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, >> if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { >> return; >> } >> - >> - /* Add a single Root port if running with defaults */ >> - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); >> } >> static void pnv_pec_realize(DeviceState *dev, Error **errp) >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index 081b6839cc..3b0b230e49 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -688,7 +688,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) >> static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) >> { >> Monitor *mon = opaque; >> - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); >> + PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); > > I'm sure this could just be: > > PnvPHB *phb = PNV_PHB(child); But it would assert if child is not of the correct type. The routine above is called from a object_child_foreach() which loops on all children. I think it could be improved by using directly &chip*->phbs[i]. C. > >> + PnvPHB4 *phb4; >> + >> + if (!phb) { >> + return 0; >> + } >> + >> + phb4 = (PnvPHB4 *)phb->backend; > > and you should be able to do: > > phb4 = PNV_PHB4(phb->backend); > > My preference for using the QOM macros where possible is that they also include a type check that assert()s if you assign the wrong type of QOM object, which a direct C cast would miss. > >> if (phb4) { >> pnv_phb4_pic_print_info(phb4, mon); >> @@ -2164,8 +2171,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) >> PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); >> static const char compat[] = "qemu,powernv9\0ibm,powernv"; >> + static GlobalProperty phb_compat[] = { >> + { TYPE_PNV_PHB, "version", "4" }, >> + }; >> + >> mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; >> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); >> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); >> + >> xfc->match_nvt = pnv_match_nvt; >> mc->alias = "powernv"; >> @@ -2182,8 +2195,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) >> XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); >> static const char compat[] = "qemu,powernv10\0ibm,powernv"; >> + static GlobalProperty phb_compat[] = { >> + { TYPE_PNV_PHB, "version", "5" }, >> + }; >> + >> mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; >> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); >> + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); >> pmc->compat = compat; >> pmc->compat_size = sizeof(compat); >> diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h >> index 90843ac3a9..f22253358f 100644 >> --- a/include/hw/pci-host/pnv_phb4.h >> +++ b/include/hw/pci-host/pnv_phb4.h >> @@ -18,6 +18,7 @@ >> typedef struct PnvPhb4PecState PnvPhb4PecState; >> typedef struct PnvPhb4PecStack PnvPhb4PecStack; >> typedef struct PnvPHB4 PnvPHB4; >> +typedef struct PnvPHB PnvPHB; >> typedef struct PnvChip PnvChip; >> /* >> @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) >> #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) >> struct PnvPHB4 { >> - PCIExpressHost parent_obj; >> + DeviceState parent; >> + >> + PnvPHB *phb_base; >> uint32_t chip_id; >> uint32_t phb_id; > > > ATB, > > Mark.
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index ae5494fe72..22cf1c2a5e 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -49,7 +49,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) { - PCIHostState *pci = PCI_HOST_BRIDGE(phb); + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; uint8_t bus, devfn; @@ -145,7 +145,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, unsigned size, uint64_t val) { - PCIHostState *pci = PCI_HOST_BRIDGE(phb); + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); PCIDevice *pdev; if (size != 4) { @@ -166,7 +166,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, unsigned size) { - PCIHostState *pci = PCI_HOST_BRIDGE(phb); + PCIHostState *pci = PCI_HOST_BRIDGE(phb->phb_base); PCIDevice *pdev; uint64_t val; @@ -1608,16 +1608,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error **errp) pnv_phb4_xscom_realize(phb); } -static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, - PCIBus *rootbus) -{ - PnvPHB4 *phb = PNV_PHB4(host_bridge); - - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", - phb->chip_id, phb->phb_id); - return phb->bus_path; -} - /* * Address base trigger mode (POWER10) * @@ -1702,19 +1692,18 @@ static Property pnv_phb4_properties[] = { DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, PnvPhb4PecState *), + DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, + TYPE_PNV_PHB, PnvPHB *), DEFINE_PROP_END_OF_LIST(), }; static void pnv_phb4_class_init(ObjectClass *klass, void *data) { - PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); - hc->root_bus_path = pnv_phb4_root_bus_path; dc->realize = pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->user_creatable = false; xfc->notify = pnv_phb4_xive_notify; @@ -1722,7 +1711,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, void *data) static const TypeInfo pnv_phb4_type_info = { .name = TYPE_PNV_PHB4, - .parent = TYPE_PCIE_HOST_BRIDGE, + .parent = TYPE_DEVICE, .instance_init = pnv_phb4_instance_init, .instance_size = sizeof(PnvPHB4), .class_init = pnv_phb4_class_init, @@ -1785,11 +1774,11 @@ static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); PCIDevice *pci = PCI_DEVICE(dev); PCIBus *bus = pci_get_bus(pci); - PnvPHB4 *phb = NULL; + PnvPHB *phb = NULL; Error *local_err = NULL; - phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB4); + phb = (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB); if (!phb) { error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 61bc0b503e..888ecbe8f3 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, int stack_no, Error **errp) { - PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); - PnvPHB4 *phb = PNV_PHB4(qdev_new(pecc->phb_type)); + PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); @@ -130,9 +129,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } - - /* Add a single Root port if running with defaults */ - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); } static void pnv_pec_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 081b6839cc..3b0b230e49 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -688,7 +688,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) { Monitor *mon = opaque; - PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); + PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); + PnvPHB4 *phb4; + + if (!phb) { + return 0; + } + + phb4 = (PnvPHB4 *)phb->backend; if (phb4) { pnv_phb4_pic_print_info(phb4, mon); @@ -2164,8 +2171,14 @@ static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); static const char compat[] = "qemu,powernv9\0ibm,powernv"; + static GlobalProperty phb_compat[] = { + { TYPE_PNV_PHB, "version", "4" }, + }; + mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); + xfc->match_nvt = pnv_match_nvt; mc->alias = "powernv"; @@ -2182,8 +2195,13 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); static const char compat[] = "qemu,powernv10\0ibm,powernv"; + static GlobalProperty phb_compat[] = { + { TYPE_PNV_PHB, "version", "5" }, + }; + mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); pmc->compat = compat; pmc->compat_size = sizeof(compat); diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 90843ac3a9..f22253358f 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -18,6 +18,7 @@ typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; typedef struct PnvPHB4 PnvPHB4; +typedef struct PnvPHB PnvPHB; typedef struct PnvChip PnvChip; /* @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) struct PnvPHB4 { - PCIExpressHost parent_obj; + DeviceState parent; + + PnvPHB *phb_base; uint32_t chip_id; uint32_t phb_id;
Change the parent type of the PnvPHB4 device to TYPE_PARENT since the PCI bus is going to be initialized by the PnvPHB parent. Functions that needs to access the bus via a PnvPHB4 object can do so via the phb4->phb_base pointer. pnv_phb4_pec now creates a PnvPHB object. The powernv9 machine class will create PnvPHB devices with version '4'. powernv10 will create using version '5'. Both are using global machine properties in their class_init() to do that. These changes will benefit us when adding PnvPHB user creatable devices for powernv9 and powernv10. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> --- hw/pci-host/pnv_phb4.c | 29 +++++++++-------------------- hw/pci-host/pnv_phb4_pec.c | 6 +----- hw/ppc/pnv.c | 20 +++++++++++++++++++- include/hw/pci-host/pnv_phb4.h | 5 ++++- 4 files changed, 33 insertions(+), 27 deletions(-)