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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id i13-20020a170902c94d00b0016362da9a03sm17853534pla.245.2022.06.09.22.13.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Jun 2022 22:13:57 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Frank Chang , Palmer Dabbelt , Alistair Francis , Bin Meng Subject: [PATCH 8/9] target/riscv: debug: Return 0 if previous value written to tselect >= number of triggers Date: Fri, 10 Jun 2022 13:13:25 +0800 Message-Id: <20220610051328.7078-9-frank.chang@sifive.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220610051328.7078-1-frank.chang@sifive.com> References: <20220610051328.7078-1-frank.chang@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang If the value written to tselect is greater than or equal to the number of supported triggers, then the following reads of tselect would return value 0. Signed-off-by: Frank Chang --- target/riscv/cpu.h | 1 + target/riscv/debug.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bac5f00722..c7ee3f80e6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -289,6 +289,7 @@ struct CPUArchState { /* trigger module */ target_ulong trigger_cur; + target_ulong trigger_prev; target_ulong tdata1[RV_MAX_TRIGGERS]; target_ulong tdata2[RV_MAX_TRIGGERS]; target_ulong tdata3[RV_MAX_TRIGGERS]; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index ce9ff15d75..83b72fa1b9 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -158,6 +158,10 @@ bool tdata_available(CPURISCVState *env, int tdata_index) target_ulong tselect_csr_read(CPURISCVState *env) { + if (env->trigger_prev >= RV_MAX_TRIGGERS) { + return 0; + } + return env->trigger_cur; } @@ -166,6 +170,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val) if (val < RV_MAX_TRIGGERS) { env->trigger_cur = val; } + + env->trigger_prev = val; } static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val,