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[144.168.56.201]) by smtp.gmail.com with ESMTPSA id j9-20020aa79289000000b0051c79bd5047sm8436945pfa.139.2022.06.14.21.08.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jun 2022 21:08:09 -0700 (PDT) From: Bin Meng To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Bin Meng Subject: [PATCH] target/riscv: Update tval for hardware watchpoint Date: Wed, 15 Jun 2022 12:08:06 +0800 Message-Id: <20220615040806.137678-1-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng When watchpoint is hit, the breakpoint exception should update tval to point to the faulting virtual address. Signed-off-by: Bin Meng --- target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 6 ++++++ target/riscv/debug.c | 2 ++ 3 files changed, 9 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7d6397acdf..fdcba8978b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -289,6 +289,7 @@ struct CPUArchState { /* trigger module */ target_ulong trigger_cur; + bool wp_hit; type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; /* machine specific rdtime callback */ diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 4a6700c890..f1564ce51e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1345,6 +1345,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong htval = 0; target_ulong mtval2 = 0; + /* only update tval for watchpoint */ + if (cause == RISCV_EXCP_BREAKPOINT && env->wp_hit) { + env->wp_hit = false; + tval = env->badaddr; + } + if (cause == RISCV_EXCP_SEMIHOST) { if (env->priv >= PRV_S) { env->gpr[xA0] = do_common_semihosting(cs); diff --git a/target/riscv/debug.c b/target/riscv/debug.c index fc6e13222f..89b12c6bef 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -407,6 +407,8 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) if ((wp->flags & flags) && (wp->vaddr == addr)) { /* check U/S/M bit against current privilege level */ if ((ctrl >> 3) & BIT(env->priv)) { + env->wp_hit = true; + env->badaddr = addr; return true; } }