diff mbox series

[1/2] target/riscv: Fixup MSECCFG minimum priv check

Message ID 20220629233102.275181-2-alistair.francis@opensource.wdc.com (mailing list archive)
State New, archived
Headers show
Series target/riscv: Fixes for Ibex and OpenTitan | expand

Commit Message

Alistair Francis June 29, 2022, 11:31 p.m. UTC
From: Alistair Francis <alistair.francis@wdc.com>

There is nothing in the RISC-V spec that mandates version 1.12 is
required for ePMP and there is currently hardware [1] that implements
ePMP (a draft version though) with the 1.11 priv spec.

1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html

Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce privilege version field in the CSR ops.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 target/riscv/csr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Bin Meng July 1, 2022, 12:32 p.m. UTC | #1
On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> There is nothing in the RISC-V spec that mandates version 1.12 is
> required for ePMP and there is currently hardware [1] that implements
> ePMP (a draft version though) with the 1.11 priv spec.
>
> 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
>
> Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce privilege version field in the CSR ops.

The format is

Fixes: 12 digits commit id ("commit title")

> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  target/riscv/csr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 6dbe9b541f..6379bef5a5 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -3561,7 +3561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
>
>      /* Physical Memory Protection */
>      [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
> -                                     .min_priv_ver = PRIV_VERSION_1_12_0 },
> +                                     .min_priv_ver = PRIV_VERSION_1_11_0 },
>      [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
>      [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
>      [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
> --
>

Other than that,
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Alistair Francis July 2, 2022, 6:53 a.m. UTC | #2
On Fri, Jul 1, 2022 at 10:32 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> On Thu, Jun 30, 2022 at 7:31 AM Alistair Francis
> <alistair.francis@opensource.wdc.com> wrote:
> >
> > From: Alistair Francis <alistair.francis@wdc.com>
> >
> > There is nothing in the RISC-V spec that mandates version 1.12 is
> > required for ePMP and there is currently hardware [1] that implements
> > ePMP (a draft version though) with the 1.11 priv spec.
> >
> > 1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
> >
> > Fixes: a4b2fa433125af0305b0695d7f8dda61db3364b0 target/riscv: Introduce privilege version field in the CSR ops.
>
> The format is
>
> Fixes: 12 digits commit id ("commit title")

Thanks! I meant to come back and fix this up but then forgot

Applied to riscv-to-apply.next

Alistair

>
> > Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >  target/riscv/csr.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> > index 6dbe9b541f..6379bef5a5 100644
> > --- a/target/riscv/csr.c
> > +++ b/target/riscv/csr.c
> > @@ -3561,7 +3561,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
> >
> >      /* Physical Memory Protection */
> >      [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
> > -                                     .min_priv_ver = PRIV_VERSION_1_12_0 },
> > +                                     .min_priv_ver = PRIV_VERSION_1_11_0 },
> >      [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
> >      [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
> >      [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },
> > --
> >
>
> Other than that,
> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6dbe9b541f..6379bef5a5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3561,7 +3561,7 @@  riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
 
     /* Physical Memory Protection */
     [CSR_MSECCFG]    = { "mseccfg",  epmp, read_mseccfg, write_mseccfg,
-                                     .min_priv_ver = PRIV_VERSION_1_12_0 },
+                                     .min_priv_ver = PRIV_VERSION_1_11_0 },
     [CSR_PMPCFG0]    = { "pmpcfg0",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG1]    = { "pmpcfg1",   pmp, read_pmpcfg,  write_pmpcfg  },
     [CSR_PMPCFG2]    = { "pmpcfg2",   pmp, read_pmpcfg,  write_pmpcfg  },