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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id l17-20020a170903121100b0016bef50c1ebsm8122412plh.128.2022.07.08.00.39.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Jul 2022 00:39:51 -0700 (PDT) From: Kito Cheng To: alistair.francis@wdc.com, palmer@dabbelt.com, frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, liweiwei@iscas.ac.cn Cc: Kito Cheng Subject: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default Date: Fri, 8 Jul 2022 15:39:43 +0800 Message-Id: <20220708073943.54781-2-kito.cheng@sifive.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20220708073943.54781-1-kito.cheng@sifive.com> References: <20220708073943.54781-1-kito.cheng@sifive.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=kito.cheng@sifive.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Default ELEN is setting to 64 for now, which is incorrect setting for Zve32*, and spec has mention minimum VLEN and supported EEW in chapter "Zve*: Vector Extensions for Embedded Processors" is 32 for Zve32. ELEN actaully could be derived from which extensions are enabled, so this patch set elen to 0 as auto detect, and keep the capability to let user could configure that. Signed-off-by: Kito Cheng --- target/riscv/cpu.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 487d0faa63..c1b96da7da 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -751,13 +751,22 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) "Vector extension ELEN must be power of 2"); return; } - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { + if (cpu->cfg.elen == 0) { + if (cpu->cfg.ext_zve32f) { + cpu->cfg.elen = 32; + } + if (cpu->cfg.ext_zve64f || cpu->cfg.ext_v) { + cpu->cfg.elen = 64; + } + } + if (cpu->cfg.elen != 0 && (cpu->cfg.elen > 64 || + cpu->cfg.elen < 8)) { error_setg(errp, "Vector extension implementation only supports ELEN " "in the range [8, 64]"); return; } - if (cpu->cfg.vlen < cpu->cfg.elen) { + if (cpu->cfg.elen != 0 && cpu->cfg.vlen < cpu->cfg.elen) { error_setg(errp, "Vector extension VLEN must be greater than or equal " "to ELEN"); @@ -901,7 +910,8 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), - DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), + /* elen = 0 means set from v or zve* extension */ + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 0), DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),