diff mbox series

[4/7] pci: designware: ignore new bits in ATU CR1

Message ID 20220713165449.37433-5-ben.dooks@sifive.com (mailing list archive)
State New, archived
Headers show
Series [1/7] pci: designware: add 64-bit viewport limit | expand

Commit Message

Ben Dooks July 13, 2022, 4:54 p.m. UTC 
In version 4 and anver ATU CR1 has more bits in it than just the
viewport type. Make a guess at masking these out to avoid issues
where Linux writes these bits and fails to enable memory ATUs.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
 hw/pci-host/designware.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c
index 6403416634..947547d153 100644
--- a/hw/pci-host/designware.c
+++ b/hw/pci-host/designware.c
@@ -276,10 +276,10 @@  static void designware_pcie_update_viewport(DesignwarePCIERoot *root,
     const uint64_t base   = viewport->base;
     const uint64_t size   = viewport->limit - base + 1;
     const bool enabled    = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE;
-
+    uint32_t cr0          = viewport->cr[0];
     MemoryRegion *current, *other;
 
-    if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) {
+    if ((cr0 & 0xFF) == DESIGNWARE_PCIE_ATU_TYPE_MEM) {
         current = &viewport->mem;
         other   = &viewport->cfg;
         memory_region_set_alias_offset(current, target);