diff mbox series

[1/1] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V

Message ID 20220717101543.478533-2-space.monkey.delivers@gmail.com (mailing list archive)
State New, archived
Headers show
Series Fix pointer masking functionality for RISC-V | expand

Commit Message

Alexey Baturo July 17, 2022, 10:15 a.m. UTC 
From: Alexey Baturo <baturo.alexey@gmail.com>

Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>
---
 target/riscv/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Alistair Francis July 19, 2022, 6:55 a.m. UTC | #1 
On Sun, Jul 17, 2022 at 8:17 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>

Fixes: 4302bef9e178 ("target/riscv: Calculate address according to XLEN")

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 63b04e8a94..86c19ea74e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -544,7 +544,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>
>      tcg_gen_addi_tl(addr, src1, imm);
>      if (ctx->pm_mask_enabled) {
> -        tcg_gen_and_tl(addr, addr, pm_mask);
> +        tcg_gen_andc_tl(addr, addr, pm_mask);
>      } else if (get_xl(ctx) == MXL_RV32) {
>          tcg_gen_ext32u_tl(addr, addr);
>      }
> --
> 2.30.2
>
>
Alistair Francis July 19, 2022, 7:06 a.m. UTC | #2 
On Sun, Jul 17, 2022 at 8:17 PM Alexey Baturo <baturo.alexey@gmail.com> wrote:
>
> From: Alexey Baturo <baturo.alexey@gmail.com>
>
> Signed-off-by: Alexey Baturo <baturo.alexey@gmail.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  target/riscv/translate.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 63b04e8a94..86c19ea74e 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -544,7 +544,7 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm)
>
>      tcg_gen_addi_tl(addr, src1, imm);
>      if (ctx->pm_mask_enabled) {
> -        tcg_gen_and_tl(addr, addr, pm_mask);
> +        tcg_gen_andc_tl(addr, addr, pm_mask);
>      } else if (get_xl(ctx) == MXL_RV32) {
>          tcg_gen_ext32u_tl(addr, addr);
>      }
> --
> 2.30.2
>
>
diff mbox series

Patch

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 63b04e8a94..86c19ea74e 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -544,7 +544,7 @@  static TCGv get_address(DisasContext *ctx, int rs1, int imm)
 
     tcg_gen_addi_tl(addr, src1, imm);
     if (ctx->pm_mask_enabled) {
-        tcg_gen_and_tl(addr, addr, pm_mask);
+        tcg_gen_andc_tl(addr, addr, pm_mask);
     } else if (get_xl(ctx) == MXL_RV32) {
         tcg_gen_ext32u_tl(addr, addr);
     }