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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id ij8-20020a170902ab4800b0016c066e566bsm8041019plb.164.2022.07.17.20.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Jul 2022 20:52:58 -0700 (PDT) From: Jim Shu To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Jim Shu , Palmer Dabbelt , Alistair Francis , Bin Meng Subject: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension Date: Mon, 18 Jul 2022 03:52:26 +0000 Message-Id: <20220718035249.17440-1-jim.shu@sifive.com> X-Mailer: git-send-email 2.17.1 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=jim.shu@sifive.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" RISC-V priv spec v1.12 permits 2 PTE-update schemes of A/D-bit (Access/Dirty bit): HW update or SW update. RISC-V profile defines the extension name 'Ssptwad' for HW update to PTE A/D bits. https://github.com/riscv/riscv-profiles/blob/main/profiles.adoc Current QEMU RISC-V implements HW update scheme, so this commit introduces SW update scheme to QEMU and uses the 'Ssptwad' extension as the CPU option to select 2 PTE-update schemes. QEMU RISC-V CPU still uses HW update scheme (ext_ssptwad=true) by default to keep the backward compatibility. SW update scheme implemention is based on priv spec v1.12: "When a virtual page is accessed and the A bit is clear, or is written and the D bit is clear, a page-fault exception (corresponding to the original access type) is raised." Signed-off-by: Jim Shu Reviewed-by: Frank Chang --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 9 +++++++++ 3 files changed, 12 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1bb3973806..1d38c1c1d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -857,6 +857,7 @@ static void riscv_cpu_init(Object *obj) cpu->cfg.ext_ifencei = true; cpu->cfg.ext_icsr = true; + cpu->cfg.ext_ssptwad = true; cpu->cfg.mmu = true; cpu->cfg.pmp = true; @@ -900,6 +901,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), + DEFINE_PROP_BOOL("ssptwad", RISCVCPU, cfg.ext_ssptwad, true), DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5c7acc055a..2eee59af98 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -433,6 +433,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zmmul; + bool ext_ssptwad; bool rvv_ta_all_1s; uint32_t mvendorid; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 59b3680b1b..a8607c0d7b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -981,6 +981,15 @@ restart: /* Page table updates need to be atomic with MTTCG enabled */ if (updated_pte != pte) { + if (!cpu->cfg.ext_ssptwad) { + /* + * If A/D bits are managed by SW, HW just raises the + * page fault exception corresponding to the original + * access type when A/D bits need to be updated. + */ + return TRANSLATE_FAIL; + } + /* * - if accessed or dirty bits need updating, and the PTE is * in RAM, then we do so atomically with a compare and swap.