diff mbox series

[V3,2/6] target/riscv: H extension depends on I extension

Message ID 20220718130955.11899-3-liweiwei@iscas.ac.cn (mailing list archive)
State New, archived
Headers show
Series Improve the U/S/H extension related check | expand

Commit Message

Weiwei Li July 18, 2022, 1:09 p.m. UTC 
Add check for "H depends on an I base integer ISA with 32 x registers"
which is stated at the beginning of chapter 8 of the riscv-privileged
spec(draft-20220717)

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
---
 target/riscv/cpu.c | 6 ++++++
 1 file changed, 6 insertions(+)
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 36c1b26fb3..b8ce0959cb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -732,6 +732,12 @@  static void riscv_cpu_realize(DeviceState *dev, Error **errp)
             return;
         }
 
+        if (cpu->cfg.ext_h && !cpu->cfg.ext_i) {
+            error_setg(errp,
+                       "H depends on an I base integer ISA with 32 x registers");
+            return;
+        }
+
         if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) {
             error_setg(errp, "F extension requires Zicsr");
             return;