diff mbox series

[14/19] ppc/ppc405: QOM'ify POB

Message ID 20220801131039.1693913-15-clg@kaod.org (mailing list archive)
State New, archived
Headers show
Series ppc: QOM'ify 405 board | expand

Commit Message

Cédric Le Goater Aug. 1, 2022, 1:10 p.m. UTC 
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/ppc/ppc405.h    | 14 +++++++++++
 hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++++++++---------------
 2 files changed, 53 insertions(+), 19 deletions(-)

Comments

Daniel Henrique Barboza Aug. 3, 2022, 9:27 a.m. UTC | #1 
On 8/1/22 10:10, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>

>   hw/ppc/ppc405.h    | 14 +++++++++++
>   hw/ppc/ppc405_uc.c | 58 +++++++++++++++++++++++++++++++---------------
>   2 files changed, 53 insertions(+), 19 deletions(-)
> 
> diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
> index ebff00bdad80..d39d65cc86e4 100644
> --- a/hw/ppc/ppc405.h
> +++ b/hw/ppc/ppc405.h
> @@ -65,6 +65,19 @@ struct ppc4xx_bd_info_t {
>   
>   typedef struct Ppc405SoCState Ppc405SoCState;
>   
> +/* PLB to OPB bridge */
> +#define TYPE_PPC405_POB "ppc405-pob"
> +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
> +struct Ppc405PobState {
> +    DeviceState parent_obj;
> +
> +    PowerPCCPU *cpu;
> +
> +    uint32_t bear;
> +    uint32_t besr0;
> +    uint32_t besr1;
> +};
> +
>   /* OPB arbitrer */
>   #define TYPE_PPC405_OPBA "ppc405-opba"
>   OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
> @@ -231,6 +244,7 @@ struct Ppc405SoCState {
>       Ppc405DmaState dma;
>       Ppc405EbcState ebc;
>       Ppc405OpbaState opba;
> +    Ppc405PobState pob;
>   };
>   
>   /* PowerPC 405 core */
> diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
> index c5de00de7981..218d911bca3c 100644
> --- a/hw/ppc/ppc405_uc.c
> +++ b/hw/ppc/ppc405_uc.c
> @@ -234,19 +234,11 @@ enum {
>       POB0_BEAR  = 0x0A4,
>   };
>   
> -typedef struct ppc4xx_pob_t ppc4xx_pob_t;
> -struct ppc4xx_pob_t {
> -    uint32_t bear;
> -    uint32_t besr0;
> -    uint32_t besr1;
> -};
> -
>   static uint32_t dcr_read_pob (void *opaque, int dcrn)
>   {
> -    ppc4xx_pob_t *pob;
> +    Ppc405PobState *pob = PPC405_POB(opaque);
>       uint32_t ret;
>   
> -    pob = opaque;
>       switch (dcrn) {
>       case POB0_BEAR:
>           ret = pob->bear;
> @@ -268,9 +260,8 @@ static uint32_t dcr_read_pob (void *opaque, int dcrn)
>   
>   static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
>   {
> -    ppc4xx_pob_t *pob;
> +    Ppc405PobState *pob = PPC405_POB(opaque);
>   
> -    pob = opaque;
>       switch (dcrn) {
>       case POB0_BEAR:
>           /* Read only */
> @@ -286,26 +277,44 @@ static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
>       }
>   }
>   
> -static void ppc4xx_pob_reset (void *opaque)
> +static void ppc405_pob_reset(DeviceState *dev)
>   {
> -    ppc4xx_pob_t *pob;
> +    Ppc405PobState *pob = PPC405_POB(dev);
>   
> -    pob = opaque;
>       /* No error */
>       pob->bear = 0x00000000;
>       pob->besr0 = 0x0000000;
>       pob->besr1 = 0x0000000;
>   }
>   
> -static void ppc4xx_pob_init(CPUPPCState *env)
> +static void ppc405_pob_realize(DeviceState *dev, Error **errp)
>   {
> -    ppc4xx_pob_t *pob;
> +    Ppc405PobState *pob = PPC405_POB(dev);
> +    CPUPPCState *env;
> +
> +    assert(pob->cpu);
> +
> +    env = &pob->cpu->env;
>   
> -    pob = g_new0(ppc4xx_pob_t, 1);
>       ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
>       ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
>       ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
> -    qemu_register_reset(ppc4xx_pob_reset, pob);
> +}
> +
> +static Property ppc405_pob_properties[] = {
> +    DEFINE_PROP_LINK("cpu", Ppc405PobState, cpu, TYPE_POWERPC_CPU,
> +                     PowerPCCPU *),
> +    DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void ppc405_pob_class_init(ObjectClass *oc, void *data)
> +{
> +    DeviceClass *dc = DEVICE_CLASS(oc);
> +
> +    dc->realize = ppc405_pob_realize;
> +    dc->user_creatable = false;
> +    dc->reset = ppc405_pob_reset;
> +    device_class_set_props(dc, ppc405_pob_properties);
>   }
>   
>   /*****************************************************************************/
> @@ -1435,6 +1444,8 @@ static void ppc405_soc_instance_init(Object *obj)
>       object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
>   
>       object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
> +
> +    object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
>   }
>   
>   static void ppc405_soc_realize(DeviceState *dev, Error **errp)
> @@ -1484,7 +1495,11 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
>       ppc4xx_plb_init(env);
>   
>       /* PLB to OPB bridge */
> -    ppc4xx_pob_init(env);
> +    object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
> +                             &error_abort);
> +    if (!qdev_realize(DEVICE(&s->pob), NULL, errp)) {
> +        return;
> +    }
>   
>       /* OBP arbitrer */
>      if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
> @@ -1602,6 +1617,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
>   
>   static const TypeInfo ppc405_types[] = {
>       {
> +        .name           = TYPE_PPC405_POB,
> +        .parent         = TYPE_DEVICE,
> +        .instance_size  = sizeof(Ppc405PobState),
> +        .class_init     = ppc405_pob_class_init,
> +    }, {
>           .name           = TYPE_PPC405_OPBA,
>           .parent         = TYPE_SYS_BUS_DEVICE,
>           .instance_size  = sizeof(Ppc405OpbaState),
diff mbox series

Patch

diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h
index ebff00bdad80..d39d65cc86e4 100644
--- a/hw/ppc/ppc405.h
+++ b/hw/ppc/ppc405.h
@@ -65,6 +65,19 @@  struct ppc4xx_bd_info_t {
 
 typedef struct Ppc405SoCState Ppc405SoCState;
 
+/* PLB to OPB bridge */
+#define TYPE_PPC405_POB "ppc405-pob"
+OBJECT_DECLARE_SIMPLE_TYPE(Ppc405PobState, PPC405_POB);
+struct Ppc405PobState {
+    DeviceState parent_obj;
+
+    PowerPCCPU *cpu;
+
+    uint32_t bear;
+    uint32_t besr0;
+    uint32_t besr1;
+};
+
 /* OPB arbitrer */
 #define TYPE_PPC405_OPBA "ppc405-opba"
 OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OpbaState, PPC405_OPBA);
@@ -231,6 +244,7 @@  struct Ppc405SoCState {
     Ppc405DmaState dma;
     Ppc405EbcState ebc;
     Ppc405OpbaState opba;
+    Ppc405PobState pob;
 };
 
 /* PowerPC 405 core */
diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c
index c5de00de7981..218d911bca3c 100644
--- a/hw/ppc/ppc405_uc.c
+++ b/hw/ppc/ppc405_uc.c
@@ -234,19 +234,11 @@  enum {
     POB0_BEAR  = 0x0A4,
 };
 
-typedef struct ppc4xx_pob_t ppc4xx_pob_t;
-struct ppc4xx_pob_t {
-    uint32_t bear;
-    uint32_t besr0;
-    uint32_t besr1;
-};
-
 static uint32_t dcr_read_pob (void *opaque, int dcrn)
 {
-    ppc4xx_pob_t *pob;
+    Ppc405PobState *pob = PPC405_POB(opaque);
     uint32_t ret;
 
-    pob = opaque;
     switch (dcrn) {
     case POB0_BEAR:
         ret = pob->bear;
@@ -268,9 +260,8 @@  static uint32_t dcr_read_pob (void *opaque, int dcrn)
 
 static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
 {
-    ppc4xx_pob_t *pob;
+    Ppc405PobState *pob = PPC405_POB(opaque);
 
-    pob = opaque;
     switch (dcrn) {
     case POB0_BEAR:
         /* Read only */
@@ -286,26 +277,44 @@  static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
     }
 }
 
-static void ppc4xx_pob_reset (void *opaque)
+static void ppc405_pob_reset(DeviceState *dev)
 {
-    ppc4xx_pob_t *pob;
+    Ppc405PobState *pob = PPC405_POB(dev);
 
-    pob = opaque;
     /* No error */
     pob->bear = 0x00000000;
     pob->besr0 = 0x0000000;
     pob->besr1 = 0x0000000;
 }
 
-static void ppc4xx_pob_init(CPUPPCState *env)
+static void ppc405_pob_realize(DeviceState *dev, Error **errp)
 {
-    ppc4xx_pob_t *pob;
+    Ppc405PobState *pob = PPC405_POB(dev);
+    CPUPPCState *env;
+
+    assert(pob->cpu);
+
+    env = &pob->cpu->env;
 
-    pob = g_new0(ppc4xx_pob_t, 1);
     ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
     ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
     ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
-    qemu_register_reset(ppc4xx_pob_reset, pob);
+}
+
+static Property ppc405_pob_properties[] = {
+    DEFINE_PROP_LINK("cpu", Ppc405PobState, cpu, TYPE_POWERPC_CPU,
+                     PowerPCCPU *),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ppc405_pob_class_init(ObjectClass *oc, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(oc);
+
+    dc->realize = ppc405_pob_realize;
+    dc->user_creatable = false;
+    dc->reset = ppc405_pob_reset;
+    device_class_set_props(dc, ppc405_pob_properties);
 }
 
 /*****************************************************************************/
@@ -1435,6 +1444,8 @@  static void ppc405_soc_instance_init(Object *obj)
     object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
 
     object_initialize_child(obj, "opba", &s->opba, TYPE_PPC405_OPBA);
+
+    object_initialize_child(obj, "pob", &s->pob, TYPE_PPC405_POB);
 }
 
 static void ppc405_soc_realize(DeviceState *dev, Error **errp)
@@ -1484,7 +1495,11 @@  static void ppc405_soc_realize(DeviceState *dev, Error **errp)
     ppc4xx_plb_init(env);
 
     /* PLB to OPB bridge */
-    ppc4xx_pob_init(env);
+    object_property_set_link(OBJECT(&s->pob), "cpu", OBJECT(&s->cpu),
+                             &error_abort);
+    if (!qdev_realize(DEVICE(&s->pob), NULL, errp)) {
+        return;
+    }
 
     /* OBP arbitrer */
    if (!sysbus_realize(SYS_BUS_DEVICE(&s->opba), errp)) {
@@ -1602,6 +1617,11 @@  static void ppc405_soc_class_init(ObjectClass *oc, void *data)
 
 static const TypeInfo ppc405_types[] = {
     {
+        .name           = TYPE_PPC405_POB,
+        .parent         = TYPE_DEVICE,
+        .instance_size  = sizeof(Ppc405PobState),
+        .class_init     = ppc405_pob_class_init,
+    }, {
         .name           = TYPE_PPC405_OPBA,
         .parent         = TYPE_SYS_BUS_DEVICE,
         .instance_size  = sizeof(Ppc405OpbaState),