diff mbox series

[1/3] hw/ssi: fixup typos in ibex_spi_host

Message ID 20220810230200.149398-1-wilfred.mallawa@opensource.wdc.com (mailing list archive)
State New, archived
Headers show
Series [1/3] hw/ssi: fixup typos in ibex_spi_host | expand

Commit Message

Wilfred Mallawa Aug. 10, 2022, 11:01 p.m. UTC 
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

This patch fixes up minor typos in ibex_spi_host

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
 hw/ssi/ibex_spi_host.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Alistair Francis Aug. 11, 2022, 7:12 a.m. UTC | #1 
On Thu, Aug 11, 2022 at 11:02 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch fixes up minor typos in ibex_spi_host
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/ssi/ibex_spi_host.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
> index d14580b409..601041d719 100644
> --- a/hw/ssi/ibex_spi_host.c
> +++ b/hw/ssi/ibex_spi_host.c
> @@ -172,7 +172,7 @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
>                          & R_INTR_STATE_SPI_EVENT_MASK;
>      int err_irq = 0, event_irq = 0;
>
> -    /* Error IRQ enabled and Error IRQ Cleared*/
> +    /* Error IRQ enabled and Error IRQ Cleared */
>      if (error_en && !err_pending) {
>          /* Event enabled, Interrupt Test Error */
>          if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
> @@ -434,7 +434,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
>      case IBEX_SPI_HOST_TXDATA:
>          /*
>           * This is a hardware `feature` where
> -         * the first word written TXDATA after init is omitted entirely
> +         * the first word written to TXDATA after init is omitted entirely
>           */
>          if (s->init_status) {
>              s->init_status = false;
> @@ -487,7 +487,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
>          break;
>      case IBEX_SPI_HOST_ERROR_STATUS:
>      /*
> -     *  Indicates that any errors that have occurred.
> +     *  Indicates any errors that have occurred.
>       *  When an error occurs, the corresponding bit must be cleared
>       *  here before issuing any further commands
>       */
> --
> 2.37.1
>
>
Andrew Jones Aug. 11, 2022, 2:24 p.m. UTC | #2 
On Thu, Aug 11, 2022 at 09:01:58AM +1000, Wilfred Mallawa wrote:
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> 
> This patch fixes up minor typos in ibex_spi_host
> 
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
>  hw/ssi/ibex_spi_host.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
> index d14580b409..601041d719 100644
> --- a/hw/ssi/ibex_spi_host.c
> +++ b/hw/ssi/ibex_spi_host.c
> @@ -172,7 +172,7 @@ static void ibex_spi_host_irq(IbexSPIHostState *s)
>                          & R_INTR_STATE_SPI_EVENT_MASK;
>      int err_irq = 0, event_irq = 0;
>  
> -    /* Error IRQ enabled and Error IRQ Cleared*/
> +    /* Error IRQ enabled and Error IRQ Cleared */
>      if (error_en && !err_pending) {
>          /* Event enabled, Interrupt Test Error */
>          if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
> @@ -434,7 +434,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
>      case IBEX_SPI_HOST_TXDATA:
>          /*
>           * This is a hardware `feature` where
> -         * the first word written TXDATA after init is omitted entirely
> +         * the first word written to TXDATA after init is omitted entirely
>           */
>          if (s->init_status) {
>              s->init_status = false;
> @@ -487,7 +487,7 @@ static void ibex_spi_host_write(void *opaque, hwaddr addr,
>          break;
>      case IBEX_SPI_HOST_ERROR_STATUS:
>      /*
> -     *  Indicates that any errors that have occurred.
> +     *  Indicates any errors that have occurred.
>       *  When an error occurs, the corresponding bit must be cleared
>       *  here before issuing any further commands
>       */
> -- 
> 2.37.1
> 
>

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
diff mbox series

Patch

diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index d14580b409..601041d719 100644
--- a/hw/ssi/ibex_spi_host.c
+++ b/hw/ssi/ibex_spi_host.c
@@ -172,7 +172,7 @@  static void ibex_spi_host_irq(IbexSPIHostState *s)
                         & R_INTR_STATE_SPI_EVENT_MASK;
     int err_irq = 0, event_irq = 0;
 
-    /* Error IRQ enabled and Error IRQ Cleared*/
+    /* Error IRQ enabled and Error IRQ Cleared */
     if (error_en && !err_pending) {
         /* Event enabled, Interrupt Test Error */
         if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) {
@@ -434,7 +434,7 @@  static void ibex_spi_host_write(void *opaque, hwaddr addr,
     case IBEX_SPI_HOST_TXDATA:
         /*
          * This is a hardware `feature` where
-         * the first word written TXDATA after init is omitted entirely
+         * the first word written to TXDATA after init is omitted entirely
          */
         if (s->init_status) {
             s->init_status = false;
@@ -487,7 +487,7 @@  static void ibex_spi_host_write(void *opaque, hwaddr addr,
         break;
     case IBEX_SPI_HOST_ERROR_STATUS:
     /*
-     *  Indicates that any errors that have occurred.
+     *  Indicates any errors that have occurred.
      *  When an error occurs, the corresponding bit must be cleared
      *  here before issuing any further commands
      */