diff mbox series

hw/riscv: opentitan: bump opentitan version

Message ID 20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com (mailing list archive)
State New, archived
Headers show
Series hw/riscv: opentitan: bump opentitan version | expand

Commit Message

Wilfred Mallawa Aug. 12, 2022, 12:52 a.m. UTC 
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>

The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c

Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies which we are currently not supporting in qemu. As of now,
the `boot_rom` has no major significance, however, would be good to
support in the future.

Tested by running utests from the latest tock [1]
(that supports this version of OT).

[1] https://github.com/tock/tock/pull/3056

Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
---
 hw/riscv/opentitan.c         | 12 ++++++++----
 include/hw/riscv/opentitan.h | 11 ++++++-----
 2 files changed, 14 insertions(+), 9 deletions(-)

Comments

Alistair Francis Aug. 12, 2022, 7:06 a.m. UTC | #1 
On Fri, Aug 12, 2022 at 10:54 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following patch updates opentitan to match the new configuration,
> as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
>
> Note: with this patch we now skip the usage of the opentitan
> `boot_rom`. The Opentitan boot rom contains hw verification
> for devies which we are currently not supporting in qemu. As of now,
> the `boot_rom` has no major significance, however, would be good to
> support in the future.
>
> Tested by running utests from the latest tock [1]
> (that supports this version of OT).
>
> [1] https://github.com/tock/tock/pull/3056
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  hw/riscv/opentitan.c         | 12 ++++++++----
>  include/hw/riscv/opentitan.h | 11 ++++++-----
>  2 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 4495a2c039..af13dbe3b1 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -29,9 +29,9 @@
>  #include "sysemu/sysemu.h"
>
>  static const MemMapEntry ibex_memmap[] = {
> -    [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
> -    [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
> -    [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
> +    [IBEX_DEV_ROM] =            {  0x00008000,   0x8000 },
> +    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
> +    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
>      [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
>      [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
>      [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
> @@ -40,6 +40,7 @@ static const MemMapEntry ibex_memmap[] = {
>      [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
>      [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
>      [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
> +    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
>      [IBEX_DEV_USBDEV] =         {  0x40150000,  0x1000  },
>      [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
>      [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
> @@ -141,7 +142,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
> -    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
> +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
> +                            &error_abort);
>      sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
>
>      /* Boot ROM */
> @@ -253,6 +255,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>          memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
>          memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
> +    create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
> +        memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
>          memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 68892cd8e5..26d960f288 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -74,6 +74,7 @@ enum {
>      IBEX_DEV_TIMER,
>      IBEX_DEV_SENSOR_CTRL,
>      IBEX_DEV_OTP_CTRL,
> +    IBEX_DEV_LC_CTRL,
>      IBEX_DEV_PWRMGR,
>      IBEX_DEV_RSTMGR,
>      IBEX_DEV_CLKMGR,
> @@ -105,11 +106,11 @@ enum {
>      IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
>      IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
>      IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
> -    IBEX_TIMER_TIMEREXPIRED0_0    = 126,
> -    IBEX_SPI_HOST0_ERR_IRQ        = 150,
> -    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 151,
> -    IBEX_SPI_HOST1_ERR_IRQ        = 152,
> -    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 153,
> +    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
> +    IBEX_SPI_HOST0_ERR_IRQ        = 151,
> +    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 152,
> +    IBEX_SPI_HOST1_ERR_IRQ        = 153,
> +    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 154,
>  };
>
>  #endif
> --
> 2.37.1
>
>
Alistair Francis Aug. 14, 2022, 10:11 p.m. UTC | #2 
On Fri, Aug 12, 2022 at 10:54 AM Wilfred Mallawa
<wilfred.mallawa@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> The following patch updates opentitan to match the new configuration,
> as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
>
> Note: with this patch we now skip the usage of the opentitan
> `boot_rom`. The Opentitan boot rom contains hw verification
> for devies which we are currently not supporting in qemu. As of now,
> the `boot_rom` has no major significance, however, would be good to
> support in the future.
>
> Tested by running utests from the latest tock [1]
> (that supports this version of OT).
>
> [1] https://github.com/tock/tock/pull/3056
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>

Thanks!

Applied to riscv-to-apply.next

Alistair

> ---
>  hw/riscv/opentitan.c         | 12 ++++++++----
>  include/hw/riscv/opentitan.h | 11 ++++++-----
>  2 files changed, 14 insertions(+), 9 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index 4495a2c039..af13dbe3b1 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -29,9 +29,9 @@
>  #include "sysemu/sysemu.h"
>
>  static const MemMapEntry ibex_memmap[] = {
> -    [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
> -    [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
> -    [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
> +    [IBEX_DEV_ROM] =            {  0x00008000,   0x8000 },
> +    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
> +    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
>      [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
>      [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
>      [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
> @@ -40,6 +40,7 @@ static const MemMapEntry ibex_memmap[] = {
>      [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
>      [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
>      [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
> +    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
>      [IBEX_DEV_USBDEV] =         {  0x40150000,  0x1000  },
>      [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
>      [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
> @@ -141,7 +142,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>                              &error_abort);
>      object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
>                              &error_abort);
> -    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
> +    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
> +                            &error_abort);
>      sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
>
>      /* Boot ROM */
> @@ -253,6 +255,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>          memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
>          memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
> +    create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
> +        memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
>          memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
>      create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index 68892cd8e5..26d960f288 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -74,6 +74,7 @@ enum {
>      IBEX_DEV_TIMER,
>      IBEX_DEV_SENSOR_CTRL,
>      IBEX_DEV_OTP_CTRL,
> +    IBEX_DEV_LC_CTRL,
>      IBEX_DEV_PWRMGR,
>      IBEX_DEV_RSTMGR,
>      IBEX_DEV_CLKMGR,
> @@ -105,11 +106,11 @@ enum {
>      IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
>      IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
>      IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
> -    IBEX_TIMER_TIMEREXPIRED0_0    = 126,
> -    IBEX_SPI_HOST0_ERR_IRQ        = 150,
> -    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 151,
> -    IBEX_SPI_HOST1_ERR_IRQ        = 152,
> -    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 153,
> +    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
> +    IBEX_SPI_HOST0_ERR_IRQ        = 151,
> +    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 152,
> +    IBEX_SPI_HOST1_ERR_IRQ        = 153,
> +    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 154,
>  };
>
>  #endif
> --
> 2.37.1
>
>
diff mbox series

Patch

diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 4495a2c039..af13dbe3b1 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -29,9 +29,9 @@ 
 #include "sysemu/sysemu.h"
 
 static const MemMapEntry ibex_memmap[] = {
-    [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
-    [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
-    [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
+    [IBEX_DEV_ROM] =            {  0x00008000,   0x8000 },
+    [IBEX_DEV_RAM] =            {  0x10000000,  0x20000 },
+    [IBEX_DEV_FLASH] =          {  0x20000000,  0x100000 },
     [IBEX_DEV_UART] =           {  0x40000000,  0x1000  },
     [IBEX_DEV_GPIO] =           {  0x40040000,  0x1000  },
     [IBEX_DEV_SPI_DEVICE] =     {  0x40050000,  0x1000  },
@@ -40,6 +40,7 @@  static const MemMapEntry ibex_memmap[] = {
     [IBEX_DEV_TIMER] =          {  0x40100000,  0x1000  },
     [IBEX_DEV_SENSOR_CTRL] =    {  0x40110000,  0x1000  },
     [IBEX_DEV_OTP_CTRL] =       {  0x40130000,  0x4000  },
+    [IBEX_DEV_LC_CTRL] =        {  0x40140000,  0x1000  },
     [IBEX_DEV_USBDEV] =         {  0x40150000,  0x1000  },
     [IBEX_DEV_SPI_HOST0] =      {  0x40300000,  0x1000  },
     [IBEX_DEV_SPI_HOST1] =      {  0x40310000,  0x1000  },
@@ -141,7 +142,8 @@  static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus,
                             &error_abort);
-    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_abort);
+    object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x20000490,
+                            &error_abort);
     sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal);
 
     /* Boot ROM */
@@ -253,6 +255,8 @@  static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
         memmap[IBEX_DEV_SENSOR_CTRL].base, memmap[IBEX_DEV_SENSOR_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.otp_ctrl",
         memmap[IBEX_DEV_OTP_CTRL].base, memmap[IBEX_DEV_OTP_CTRL].size);
+    create_unimplemented_device("riscv.lowrisc.ibex.lc_ctrl",
+        memmap[IBEX_DEV_LC_CTRL].base, memmap[IBEX_DEV_LC_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
         memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index 68892cd8e5..26d960f288 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -74,6 +74,7 @@  enum {
     IBEX_DEV_TIMER,
     IBEX_DEV_SENSOR_CTRL,
     IBEX_DEV_OTP_CTRL,
+    IBEX_DEV_LC_CTRL,
     IBEX_DEV_PWRMGR,
     IBEX_DEV_RSTMGR,
     IBEX_DEV_CLKMGR,
@@ -105,11 +106,11 @@  enum {
     IBEX_UART0_RX_BREAK_ERR_IRQ   = 6,
     IBEX_UART0_RX_TIMEOUT_IRQ     = 7,
     IBEX_UART0_RX_PARITY_ERR_IRQ  = 8,
-    IBEX_TIMER_TIMEREXPIRED0_0    = 126,
-    IBEX_SPI_HOST0_ERR_IRQ        = 150,
-    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 151,
-    IBEX_SPI_HOST1_ERR_IRQ        = 152,
-    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 153,
+    IBEX_TIMER_TIMEREXPIRED0_0    = 127,
+    IBEX_SPI_HOST0_ERR_IRQ        = 151,
+    IBEX_SPI_HOST0_SPI_EVENT_IRQ  = 152,
+    IBEX_SPI_HOST1_ERR_IRQ        = 153,
+    IBEX_SPI_HOST1_SPI_EVENT_IRQ  = 154,
 };
 
 #endif