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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id f8-20020a2eb5a8000000b0025e72aae6bdsm356151ljn.28.2022.08.12.06.13.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Aug 2022 06:13:09 -0700 (PDT) From: Philipp Tomsich To: qemu-devel@nongnu.org Cc: Philipp Tomsich , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-riscv@nongnu.org Subject: [PATCH 2/2] target/riscv: fence: reconcile with specification Date: Fri, 12 Aug 2022 15:13:04 +0200 Message-Id: <20220812131304.1674484-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220812131304.1674484-1-philipp.tomsich@vrull.eu> References: <20220812131304.1674484-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22b; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lj1-x22b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Our decoding of fence-instructions is problematic in respect to the RISC-V ISA specification: - rs and rd are ignored, but need to be 0 - fm is ignored This change adjusts the decode pattern to enfore rs and rd being 0, and validates the fm-field (together with pred/succ for FENCE.TSO) to determine whether a reserved instruction is specified. While the specification allows UNSPECIFIED behaviour for reserved instructions, we now always raise an illegal instruction exception. Signed-off-by: Philipp Tomsich --- target/riscv/insn32.decode | 2 +- target/riscv/insn_trans/trans_rvi.c.inc | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 089128c3dc..4e53df1b62 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -150,7 +150,7 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r sra 0100000 ..... ..... 101 ..... 0110011 @r or 0000000 ..... ..... 110 ..... 0110011 @r and 0000000 ..... ..... 111 ..... 0110011 @r -fence ---- pred:4 succ:4 ----- 000 ----- 0001111 +fence fm:4 pred:4 succ:4 00000 000 00000 0001111 fence_i 000000000000 00000 001 00000 0001111 csrrw ............ ..... 001 ..... 1110011 @csr csrrs ............ ..... 010 ..... 1110011 @csr diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index ca8e3d1ea1..515bb3b22a 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -795,7 +795,24 @@ static bool trans_srad(DisasContext *ctx, arg_srad *a) static bool trans_fence(DisasContext *ctx, arg_fence *a) { - /* FENCE is a full memory barrier. */ + switch (a->fm) { + case 0b0000: + /* normal fence */ + break; + + case 0b0001: + /* FENCE.TSO requires PRED and SUCC to be RW */ + if (a->pred != 0xb0011 || a->succ != 0b0011) { + return false; + } + break; + + default: + /* reserved for future use */ + return false; + } + + /* We implement FENCE(.TSO) is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); return true; }