| Message ID | 20220816045408.1231135-1-rpathak@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] target/riscv: Add xicondops in ISA entry | expand |
On Tue, Aug 16, 2022 at 2:54 PM Rahul Pathak <rpathak@ventanamicro.com> wrote: > > XVentanaCondOps is Ventana custom extension. Add > its extension entry in the ISA Ext array > > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > This patch is based on branch riscv-to-apply.next (Alistair qemu tree) > Based on top commit: f2a91d8b78 > > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 2498b93105..27d10bd6a6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -104,6 +104,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), > }; > > static bool isa_ext_is_enabled(RISCVCPU *cpu, > -- > 2.34.1 > >
On Tue, Aug 16, 2022 at 2:54 PM Rahul Pathak <rpathak@ventanamicro.com> wrote: > > XVentanaCondOps is Ventana custom extension. Add > its extension entry in the ISA Ext array > > Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > > This patch is based on branch riscv-to-apply.next (Alistair qemu tree) > Based on top commit: f2a91d8b78 > > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 2498b93105..27d10bd6a6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -104,6 +104,7 @@ static const struct isa_ext_data isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), > }; > > static bool isa_ext_is_enabled(RISCVCPU *cpu, > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2498b93105..27d10bd6a6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -104,6 +104,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; static bool isa_ext_is_enabled(RISCVCPU *cpu,
XVentanaCondOps is Ventana custom extension. Add its extension entry in the ISA Ext array Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> --- This patch is based on branch riscv-to-apply.next (Alistair qemu tree) Based on top commit: f2a91d8b78 target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+)