Message ID | 20220817074802.20765-2-liuyang22@iscas.ac.cn (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [1/2] target/riscv: rvv-1.0: Simplify vfwredsum code | expand |
On Thu, Aug 18, 2022 at 1:43 AM Yang Liu <liuyang22@iscas.ac.cn> wrote: > > Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed > to vf[w]redusum_vs. The distinction between ordered and unordered is also > more consistent with other instructions, although there is no difference > in implementation between the two for QEMU. > > Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/helper.h | 15 ++++++++++----- > target/riscv/insn32.decode | 6 ++++-- > target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++-- > target/riscv/vector_helper.c | 19 +++++++++++++------ > 4 files changed, 31 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 4ef3b2251d..a03014fe67 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1009,9 +1009,12 @@ DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > > -DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > @@ -1019,8 +1022,10 @@ DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > > -DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > > DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 4033565393..2873a7ae04 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -659,11 +659,13 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm > vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm > vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm > # Vector ordered and unordered reduction sum > -vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm > +vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm > vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm > vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm > # Vector widening ordered and unordered float reduction sum > -vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm > +vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm > vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r > vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r > vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 6c091824b6..9c9de17f8a 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3112,7 +3112,8 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a) > require_zve64f(s); > } > > -GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) > +GEN_OPFVV_TRANS(vfredusum_vs, freduction_check) > +GEN_OPFVV_TRANS(vfredosum_vs, freduction_check) > GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) > GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) > > @@ -3124,7 +3125,8 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) > (s->sew != MO_8); > } > > -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) > +GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check) > +GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, freduction_widen_check) > > /* > *** Vector Mask Operations > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index fd83c0b20b..d87f79ad82 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4641,9 +4641,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > } > > /* Unordered sum */ > -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > +GEN_VEXT_FRED(vfredusum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > +GEN_VEXT_FRED(vfredusum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > +GEN_VEXT_FRED(vfredusum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > + > +/* Ordered sum */ > +GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > +GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > +GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > > /* Maximum value */ > GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number) > @@ -4667,9 +4672,11 @@ static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s) > } > > /* Vector Widening Floating-Point Reduction Instructions */ > -/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ > -GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > -GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > +/* Ordered/unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ > +GEN_VEXT_FRED(vfwredusum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > +GEN_VEXT_FRED(vfwredusum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > +GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > +GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > > /* > *** Vector Mask Operations > -- > 2.30.1 (Apple Git-130) > >
Reviewed-by: Frank Chang <frank.chang@sifive.com> On Wed, Aug 17, 2022 at 11:45 PM Yang Liu <liuyang22@iscas.ac.cn> wrote: > Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed > to vf[w]redusum_vs. The distinction between ordered and unordered is also > more consistent with other instructions, although there is no difference > in implementation between the two for QEMU. > > Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> > --- > target/riscv/helper.h | 15 ++++++++++----- > target/riscv/insn32.decode | 6 ++++-- > target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++-- > target/riscv/vector_helper.c | 19 +++++++++++++------ > 4 files changed, 31 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 4ef3b2251d..a03014fe67 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1009,9 +1009,12 @@ DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, > ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > > -DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > @@ -1019,8 +1022,10 @@ DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, > ptr, env, i32) > DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > > -DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > > DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 4033565393..2873a7ae04 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -659,11 +659,13 @@ vredmax_vs 000111 . ..... ..... 010 ..... > 1010111 @r_vm > vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm > vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm > # Vector ordered and unordered reduction sum > -vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm > +vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm > vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm > vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm > # Vector widening ordered and unordered float reduction sum > -vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm > +vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm > vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r > vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r > vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc > b/target/riscv/insn_trans/trans_rvv.c.inc > index 6c091824b6..9c9de17f8a 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3112,7 +3112,8 @@ static bool freduction_check(DisasContext *s, > arg_rmrr *a) > require_zve64f(s); > } > > -GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) > +GEN_OPFVV_TRANS(vfredusum_vs, freduction_check) > +GEN_OPFVV_TRANS(vfredosum_vs, freduction_check) > GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) > GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) > > @@ -3124,7 +3125,8 @@ static bool freduction_widen_check(DisasContext *s, > arg_rmrr *a) > (s->sew != MO_8); > } > > -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) > +GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check) > +GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, freduction_widen_check) > > /* > *** Vector Mask Operations > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index fd83c0b20b..d87f79ad82 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4641,9 +4641,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, > \ > } > > /* Unordered sum */ > -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > +GEN_VEXT_FRED(vfredusum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > +GEN_VEXT_FRED(vfredusum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > +GEN_VEXT_FRED(vfredusum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > + > +/* Ordered sum */ > +GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > +GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > +GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > > /* Maximum value */ > GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, > float16_maximum_number) > @@ -4667,9 +4672,11 @@ static uint64_t fwadd32(uint64_t a, uint32_t b, > float_status *s) > } > > /* Vector Widening Floating-Point Reduction Instructions */ > -/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ > -GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > -GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > +/* Ordered/unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ > +GEN_VEXT_FRED(vfwredusum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > +GEN_VEXT_FRED(vfwredusum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > +GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > +GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > > /* > *** Vector Mask Operations > -- > 2.30.1 (Apple Git-130) > > >
On Thu, Aug 18, 2022 at 1:43 AM Yang Liu <liuyang22@iscas.ac.cn> wrote: > > Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed > to vf[w]redusum_vs. The distinction between ordered and unordered is also > more consistent with other instructions, although there is no difference > in implementation between the two for QEMU. > > Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/helper.h | 15 ++++++++++----- > target/riscv/insn32.decode | 6 ++++-- > target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++-- > target/riscv/vector_helper.c | 19 +++++++++++++------ > 4 files changed, 31 insertions(+), 15 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 4ef3b2251d..a03014fe67 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -1009,9 +1009,12 @@ DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > > -DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredusum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > @@ -1019,8 +1022,10 @@ DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) > > -DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > -DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) > +DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) > > DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) > DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode > index 4033565393..2873a7ae04 100644 > --- a/target/riscv/insn32.decode > +++ b/target/riscv/insn32.decode > @@ -659,11 +659,13 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm > vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm > vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm > # Vector ordered and unordered reduction sum > -vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm > +vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm > vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm > vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm > # Vector widening ordered and unordered float reduction sum > -vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm > +vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm > +vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm > vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r > vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r > vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 6c091824b6..9c9de17f8a 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -3112,7 +3112,8 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a) > require_zve64f(s); > } > > -GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) > +GEN_OPFVV_TRANS(vfredusum_vs, freduction_check) > +GEN_OPFVV_TRANS(vfredosum_vs, freduction_check) > GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) > GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) > > @@ -3124,7 +3125,8 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) > (s->sew != MO_8); > } > > -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) > +GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check) > +GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, freduction_widen_check) > > /* > *** Vector Mask Operations > diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c > index fd83c0b20b..d87f79ad82 100644 > --- a/target/riscv/vector_helper.c > +++ b/target/riscv/vector_helper.c > @@ -4641,9 +4641,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ > } > > /* Unordered sum */ > -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > +GEN_VEXT_FRED(vfredusum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > +GEN_VEXT_FRED(vfredusum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > +GEN_VEXT_FRED(vfredusum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > + > +/* Ordered sum */ > +GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) > +GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) > +GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) > > /* Maximum value */ > GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number) > @@ -4667,9 +4672,11 @@ static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s) > } > > /* Vector Widening Floating-Point Reduction Instructions */ > -/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ > -GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > -GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > +/* Ordered/unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ > +GEN_VEXT_FRED(vfwredusum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > +GEN_VEXT_FRED(vfwredusum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > +GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) > +GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) > > /* > *** Vector Mask Operations > -- > 2.30.1 (Apple Git-130) > >
diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4ef3b2251d..a03014fe67 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1009,9 +1009,12 @@ DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vfredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vfredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vfredsum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredusum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfredosum_vs_d, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmax_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmax_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32) @@ -1019,8 +1022,10 @@ DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) -DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredusum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredusum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredosum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredosum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmand_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnand_mm, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4033565393..2873a7ae04 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -659,11 +659,13 @@ vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm # Vector ordered and unordered reduction sum -vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm +vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm +vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm # Vector widening ordered and unordered float reduction sum -vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm +vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm +vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index 6c091824b6..9c9de17f8a 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3112,7 +3112,8 @@ static bool freduction_check(DisasContext *s, arg_rmrr *a) require_zve64f(s); } -GEN_OPFVV_TRANS(vfredsum_vs, freduction_check) +GEN_OPFVV_TRANS(vfredusum_vs, freduction_check) +GEN_OPFVV_TRANS(vfredosum_vs, freduction_check) GEN_OPFVV_TRANS(vfredmax_vs, freduction_check) GEN_OPFVV_TRANS(vfredmin_vs, freduction_check) @@ -3124,7 +3125,8 @@ static bool freduction_widen_check(DisasContext *s, arg_rmrr *a) (s->sew != MO_8); } -GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, freduction_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwredusum_vs, freduction_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwredosum_vs, freduction_widen_check) /* *** Vector Mask Operations diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index fd83c0b20b..d87f79ad82 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4641,9 +4641,14 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ } /* Unordered sum */ -GEN_VEXT_FRED(vfredsum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) -GEN_VEXT_FRED(vfredsum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) -GEN_VEXT_FRED(vfredsum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) +GEN_VEXT_FRED(vfredusum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) +GEN_VEXT_FRED(vfredusum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) +GEN_VEXT_FRED(vfredusum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) + +/* Ordered sum */ +GEN_VEXT_FRED(vfredosum_vs_h, uint16_t, uint16_t, H2, H2, float16_add) +GEN_VEXT_FRED(vfredosum_vs_w, uint32_t, uint32_t, H4, H4, float32_add) +GEN_VEXT_FRED(vfredosum_vs_d, uint64_t, uint64_t, H8, H8, float64_add) /* Maximum value */ GEN_VEXT_FRED(vfredmax_vs_h, uint16_t, uint16_t, H2, H2, float16_maximum_number) @@ -4667,9 +4672,11 @@ static uint64_t fwadd32(uint64_t a, uint32_t b, float_status *s) } /* Vector Widening Floating-Point Reduction Instructions */ -/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ -GEN_VEXT_FRED(vfwredsum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) -GEN_VEXT_FRED(vfwredsum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) +/* Ordered/unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */ +GEN_VEXT_FRED(vfwredusum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) +GEN_VEXT_FRED(vfwredusum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) +GEN_VEXT_FRED(vfwredosum_vs_h, uint32_t, uint16_t, H4, H2, fwadd16) +GEN_VEXT_FRED(vfwredosum_vs_w, uint64_t, uint32_t, H8, H4, fwadd32) /* *** Vector Mask Operations
Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed to vf[w]redusum_vs. The distinction between ordered and unordered is also more consistent with other instructions, although there is no difference in implementation between the two for QEMU. Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> --- target/riscv/helper.h | 15 ++++++++++----- target/riscv/insn32.decode | 6 ++++-- target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++-- target/riscv/vector_helper.c | 19 +++++++++++++------ 4 files changed, 31 insertions(+), 15 deletions(-)