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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Marcel Apfelbaum Subject: [PULL 10/10] virtio-pci: don't touch pci on virtio reset Message-ID: <20220817161342.240674-11-mst@redhat.com> References: <20220817161342.240674-1-mst@redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220817161342.240674-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -9 X-Spam_score: -1.0 X-Spam_bar: - X-Spam_report: (-1.0 / 5.0 requ) DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" virtio level reset should not affect pci express registers such as PM, error or link. Fixes: 27ce0f3afc ("hw/virtio: fix Power Management Control Register for PCI Express virtio devices") Fixes: d584f1b9ca ("hw/virtio: fix Link Control Register for PCI Express virtio devices") Fixes: c2cabb3422 ("hw/virtio: fix error enabling flags in Device Control register") Cc: "Marcel Apfelbaum" Signed-off-by: Michael S. Tsirkin --- hw/virtio/virtio-pci.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 5ce61f9b45..a50c5a57d7 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1947,7 +1947,6 @@ static void virtio_pci_reset(DeviceState *qdev) { VirtIOPCIProxy *proxy = VIRTIO_PCI(qdev); VirtioBusState *bus = VIRTIO_BUS(&proxy->bus); - PCIDevice *dev = PCI_DEVICE(qdev); int i; virtio_bus_reset(bus); @@ -1960,6 +1959,13 @@ static void virtio_pci_reset(DeviceState *qdev) proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0; proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0; } +} + +static void virtio_pci_bus_reset(DeviceState *qdev) +{ + PCIDevice *dev = PCI_DEVICE(qdev); + + virtio_pci_reset(qdev); if (pci_is_express(dev)) { pcie_cap_deverr_reset(dev); @@ -2027,7 +2033,7 @@ static void virtio_pci_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_OTHERS; device_class_set_parent_realize(dc, virtio_pci_dc_realize, &vpciklass->parent_dc_realize); - dc->reset = virtio_pci_reset; + dc->reset = virtio_pci_bus_reset; } static const TypeInfo virtio_pci_info = {