Message ID | 20220820141914.217399-4-tobias.roehmel@rwth-aachen.de (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | Add ARM Cortex-R52 cpu | expand |
On Sat, 20 Aug 2022 at 15:19, <tobias.roehmel@rwth-aachen.de> wrote: > > From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> > > RVBAR shadows RVBAR_ELx where x is the highest exception > level if the highest EL is not EL3. This patch also allows > ARMv8 CPUs to change the reset address to be changed with > the rvbar property. > > Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de> > diff --git a/target/arm/helper.c b/target/arm/helper.c > index b9547594ae..23461397e0 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -7954,13 +7954,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) > /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ > if (!arm_feature(env, ARM_FEATURE_EL3) && > !arm_feature(env, ARM_FEATURE_EL2)) { > - ARMCPRegInfo rvbar = { > - .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, > - .access = PL1_R, > - .fieldoffset = offsetof(CPUARMState, cp15.rvbar), > + ARMCPRegInfo rvbar[] = { > + { > + .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, > + .access = PL1_R, > + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), > + }, > + { .name = "RVBAR", .type = ARM_CP_ALIAS, > + .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, > + .access = PL1_R, > + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), > + }, Because the encodings here match, you don't need a separate struct for the AArch32 RVBAR -- you can just change the ARM_CP_STATE_AA64 to ARM_CP_STATE_BOTH. > }; > - define_one_arm_cp_reg(cpu, &rvbar); > + define_arm_cp_regs(cpu, rvbar); > } > define_arm_cp_regs(cpu, v8_idregs); > define_arm_cp_regs(cpu, v8_cp_reginfo); > @@ -8022,13 +8029,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) > } > /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ > if (!arm_feature(env, ARM_FEATURE_EL3)) { > - ARMCPRegInfo rvbar = { > - .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, > - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, > - .access = PL2_R, > - .fieldoffset = offsetof(CPUARMState, cp15.rvbar), > + ARMCPRegInfo rvbar[] = { > + { > + .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, > + .access = PL2_R, > + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), > + }, > + { .name = "RVBAR", .type = ARM_CP_ALIAS, > + .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, > + .access = PL2_R, > + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), > + }, (Here we do need the second struct, beacuse the opc1 fields don't line up.) Preferred ordering for the encoding fields in a cp struct is .cp .opc1 .crn .crm .opc2 (ie in order as used in the asm instruction). Otherwise this patch looks good. thanks -- PMM
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b5d535788..9007768418 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -258,6 +258,10 @@ static void arm_cpu_reset(DeviceState *dev) env->cp15.cpacr_el1 = FIELD_DP64(env->cp15.cpacr_el1, CPACR, CP11, 3); #endif + if (arm_feature(env, ARM_FEATURE_V8)) { + env->cp15.rvbar = cpu->rvbar_prop; + env->regs[15] = cpu->rvbar_prop; + } } #if defined(CONFIG_USER_ONLY) @@ -1273,7 +1277,7 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property); } - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + if (arm_feature(&cpu->env, ARM_FEATURE_V8)) { object_property_add_uint64_ptr(obj, "rvbar", &cpu->rvbar_prop, OBJ_PROP_FLAG_READWRITE); diff --git a/target/arm/helper.c b/target/arm/helper.c index b9547594ae..23461397e0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7954,13 +7954,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { - ARMCPRegInfo rvbar = { - .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, - .access = PL1_R, - .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + ARMCPRegInfo rvbar[] = { + { + .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1, + .access = PL1_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, + { .name = "RVBAR", .type = ARM_CP_ALIAS, + .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL1_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, }; - define_one_arm_cp_reg(cpu, &rvbar); + define_arm_cp_regs(cpu, rvbar); } define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); @@ -8022,13 +8029,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) } /* RVBAR_EL2 is only implemented if EL2 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3)) { - ARMCPRegInfo rvbar = { - .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, - .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, - .access = PL2_R, - .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + ARMCPRegInfo rvbar[] = { + { + .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1, + .access = PL2_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, + { .name = "RVBAR", .type = ARM_CP_ALIAS, + .cp = 15, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 1, + .access = PL2_R, + .fieldoffset = offsetof(CPUARMState, cp15.rvbar), + }, }; - define_one_arm_cp_reg(cpu, &rvbar); + define_arm_cp_regs(cpu, rvbar); } }