| Message ID | 20220901131756.26060-8-victor.colombo@eldorado.org.br (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Multiple ppc instructions fixes | expand |
On 9/1/22 10:17, Víctor Colombo wrote: > FPR register are mapped to the first doubleword of the VSR registers. > Since PowerISA v3.1, the second doubleword of the target register > must be zeroed for FP instructions. > > This patch does it by writting 0 to the second dw everytime the > first dw is being written using set_fpr. > > Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> > --- Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> > target/ppc/translate.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/target/ppc/translate.c b/target/ppc/translate.c > index 388337f81b..a0fa419a1f 100644 > --- a/target/ppc/translate.c > +++ b/target/ppc/translate.c > @@ -6443,6 +6443,14 @@ static inline void get_fpr(TCGv_i64 dst, int regno) > static inline void set_fpr(int regno, TCGv_i64 src) > { > tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); > + /* > + * Before PowerISA v3.1 the result of doubleword 1 of the VSR > + * corresponding to the target FPR was undefined. However, > + * most (if not all) real hardware were setting the result to 0. > + * Starting at ISA v3.1, the result for doubleword 1 is now defined > + * to be 0. > + */ > + tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); > } > > static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 388337f81b..a0fa419a1f 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -6443,6 +6443,14 @@ static inline void get_fpr(TCGv_i64 dst, int regno) static inline void set_fpr(int regno, TCGv_i64 src) { tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); + /* + * Before PowerISA v3.1 the result of doubleword 1 of the VSR + * corresponding to the target FPR was undefined. However, + * most (if not all) real hardware were setting the result to 0. + * Starting at ISA v3.1, the result for doubleword 1 is now defined + * to be 0. + */ + tcg_gen_st_i64(tcg_constant_i64(0), cpu_env, vsr64_offset(regno, false)); } static inline void get_avr64(TCGv_i64 dst, int regno, bool high)
FPR register are mapped to the first doubleword of the VSR registers. Since PowerISA v3.1, the second doubleword of the target register must be zeroed for FP instructions. This patch does it by writting 0 to the second dw everytime the first dw is being written using set_fpr. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> --- target/ppc/translate.c | 8 ++++++++ 1 file changed, 8 insertions(+)