[05/11] RISC-V: Adding T-Head CondMov instructions

Commit Message

Christoph Müllner Sept. 6, 2022, 12:22 p.m. UTC

From: Christoph Müllner <[e-mail]>

This patch adds support for the T-Head CondMov instructions.
The patch uses the T-Head specific decoder and translation.

Signed-off-by: Christoph Müllner <[e-mail]>
---
 target/riscv/cpu.c                         |  1 +
 target/riscv/cpu.h                         |  1 +
 target/riscv/insn_trans/trans_xthead.c.inc | 23 +++++++++++++++
 target/riscv/meson.build                   |  1 +
 target/riscv/translate.c                   |  3 ++
 target/riscv/xtheadcondmov.decode          | 33 ++++++++++++++++++++++
 6 files changed, 62 insertions(+)
 create mode 100644 target/riscv/xtheadcondmov.decode

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d129a6112a..b7d6dbd28e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -924,6 +924,7 @@  static Property riscv_cpu_extensions[] = {
     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
+    DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
 
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 9e2b3d6f56..0b58b38335 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -444,6 +444,7 @@  struct RISCVCPUConfig {
     bool ext_xtheadbb;
     bool ext_xtheadbs;
     bool ext_xtheadcmo;
+    bool ext_xtheadcondmov;
     bool ext_xtheadsync;
     bool ext_XVentanaCondOps;
 
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc
index b2d523b905..da3a538400 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -194,3 +194,26 @@  static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a)
     return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext);
 }
 
+static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond)
+{
+    TCGv dest = dest_gpr(ctx, a->rd);
+    TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
+    TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
+
+    tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, dest);
+
+    gen_set_gpr(ctx, a->rd, dest);
+    return true;
+}
+
+/* th.mveqz: "if (rs2 == 0) rd = rs1;" */
+static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a)
+{
+    return gen_th_condmove(ctx, a, TCG_COND_EQ);
+}
+
+/* th.mvnez: "if (rs2 != 0) rd = rs1;" */
+static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a)
+{
+    return gen_th_condmove(ctx, a, TCG_COND_NE);
+}
diff --git a/target/riscv/meson.build b/target/riscv/meson.build
index 5ee37683cb..496ae37f26 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -6,6 +6,7 @@  gen = [
   decodetree.process('xtheadbb.decode', extra_args: '--static-decode=decode_xtheadbb'),
   decodetree.process('xtheadbs.decode', extra_args: '--static-decode=decode_xtheadbs'),
   decodetree.process('xtheadcmo.decode', extra_args: '--static-decode=decode_xtheadcmo'),
+  decodetree.process('xtheadcondmov.decode', extra_args: '--static-decode=decode_xtheadcondmov'),
   decodetree.process('xtheadsync.decode', extra_args: '--static-decode=decode_xtheadsync'),
   decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'),
 ]
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index f662e403f8..986243df99 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -136,6 +136,7 @@  MATERIALISE_EXT_PREDICATE(xtheadba)
 MATERIALISE_EXT_PREDICATE(xtheadbb)
 MATERIALISE_EXT_PREDICATE(xtheadbs)
 MATERIALISE_EXT_PREDICATE(xtheadcmo)
+MATERIALISE_EXT_PREDICATE(xtheadcondmov);
 MATERIALISE_EXT_PREDICATE(xtheadsync)
 MATERIALISE_EXT_PREDICATE(XVentanaCondOps)
 
@@ -727,6 +728,7 @@  static int ex_rvc_shifti(DisasContext *ctx, int imm)
 #include "decode-xtheadbb.c.inc"
 #include "decode-xtheadbs.c.inc"
 #include "decode-xtheadcmo.c.inc"
+#include "decode-xtheadcondmov.c.inc"
 #include "decode-xtheadsync.c.inc"
 #include "decode-XVentanaCondOps.c.inc"
 
@@ -1052,6 +1054,7 @@  static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
         { has_xtheadbb_p, decode_xtheadbb },
         { has_xtheadbs_p, decode_xtheadbs },
         { has_xtheadcmo_p, decode_xtheadcmo },
+        { has_xtheadcondmov_p, decode_xtheadcondmov },
         { has_xtheadsync_p, decode_xtheadsync },
         { has_XVentanaCondOps_p,  decode_XVentanaCodeOps },
     };
diff --git a/target/riscv/xtheadcondmov.decode b/target/riscv/xtheadcondmov.decode
new file mode 100644
index 0000000000..00f9ca96c6
--- /dev/null
+++ b/target/riscv/xtheadcondmov.decode
@@ -0,0 +1,33 @@ 
+#
+# RISC-V instruction decode for the XTheadCondMov extension
+#
+# Copyright (c) 2022 Dr. Philipp Tomsich, [e-mail]
+#                    Christoph Muellner, [e-mail]
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+# The XTheadCondMov extension provides conditional move instructions.
+#
+# It is documented in
+# https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf
+#
+# The instructions contained in XTheadCondMov are:
+# - th.mveqz      move to register, if condition is zero
+# - th.mvnez      move to register, if condition is non-zero
+#
+# These instructions reuse existing instruction formats.
+
+# Fields
+%rs2       20:5
+%rs1       15:5
+%rd        7:5
+
+# Argument sets
+&r         rd rs1 rs2		!extern
+
+# Formats:
+@r          ....... ..... .....  ... ..... ....... &r %rs2 %rs1 %rd
+
+# T-Head conditional move instructions
+th_mveqz    0100000 ..... .....  001 ..... 0001011 @r
+th_mvnez    0100001 ..... .....  001 ..... 0001011 @r