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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:57 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?utf-8?q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 07/11] RISC-V: Adding T-Head XMAE support Date: Tue, 6 Sep 2022 14:22:39 +0200 Message-Id: <20220906122243.1243354-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220906122243.1243354-1-christoph.muellner@vrull.eu> References: <20220906122243.1243354-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Christoph Müllner This patch adds support for the T-Head specific extended memory attributes. Similar like Svpbmt, this support does not have much effect as most behaviour is not modelled in QEMU. We also don't set any EDATA information, because XMAE discovery is done using the vendor ID in the Linux kernel. Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + target/riscv/cpu_helper.c | 6 ++++-- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e2d74fa701..990a1f57af 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -927,6 +927,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), + DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0dc4ab031..1982d9293f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -447,6 +447,7 @@ struct RISCVCPUConfig { bool ext_xtheadcondmov; bool ext_xtheadmac; bool ext_xtheadsync; + bool ext_xtheadxmae; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 59b3680b1b..d7941e64e1 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -927,7 +927,8 @@ restart: if (riscv_cpu_sxl(env) == MXL_RV32) { ppn = pte >> PTE_PPN_SHIFT; - } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { + } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot || + cpu->cfg.ext_xtheadxmae) { ppn = (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; } else { ppn = pte >> PTE_PPN_SHIFT; @@ -939,7 +940,8 @@ restart: if (!(pte & PTE_V)) { /* Invalid PTE */ return TRANSLATE_FAIL; - } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT) && + !cpu->cfg.ext_xtheadxmae) { return TRANSLATE_FAIL; } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { /* Inner PTE, continue walking */